fd267082ee
Create an empty VPlan first, then let the HCFG builder create a plain
CFG for the top-level loop (w/o a top-level region). The top-level
region is introduced by a separate VPlan-transform. This is instead of
creating the vector loop region before building the VPlan CFG for the
input loop.
This simplifies the HCFG builder (which should probably be renamed) and
moves along the roadmap ('buildLoop') outlined in [1].
As follow-up, I plan to also preserve the exit branches in the initial
VPlan out of the CFG builder, including connections to the exit blocks.
The conversion from plain CFG with potentially multiple exits to a
single entry/exit region will be done as VPlan transform in a follow-up.
This is needed to enable VPlan-based predication. Currently early exit
support relies on building the block-in masks on the original CFG,
because exiting branches and conditions aren't preserved in the VPlan.
So in order to switch to VPlan-based predication, we will have to
preserve them in the initial plain CFG, so the exit conditions are
available explicitly when we convert to single entry/exit regions.
Another follow-up is updating the outer loop handling to also introduce
VPRegionBlocks for nested loops as transform. Currently the existing
logic in the builder will take care of creating VPRegionBlocks for
nested loops, but not the top-level loop.
[1]
https://llvm.org/devmtg/2023-10/slides/techtalks/Hahn-VPlan-StatusUpdateAndRoadmap.pdf
PR: https://github.com/llvm/llvm-project/pull/128419
477 lines
18 KiB
C++
477 lines
18 KiB
C++
//===-- VPlanHCFGBuilder.cpp ----------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file implements the construction of a VPlan-based Hierarchical CFG
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/// (H-CFG) for an incoming IR. This construction comprises the following
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/// components and steps:
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//
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/// 1. PlainCFGBuilder class: builds a plain VPBasicBlock-based CFG that
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/// faithfully represents the CFG in the incoming IR. A VPRegionBlock (Top
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/// Region) is created to enclose and serve as parent of all the VPBasicBlocks
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/// in the plain CFG.
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/// NOTE: At this point, there is a direct correspondence between all the
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/// VPBasicBlocks created for the initial plain CFG and the incoming
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/// BasicBlocks. However, this might change in the future.
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///
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//===----------------------------------------------------------------------===//
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#include "VPlanHCFGBuilder.h"
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#include "LoopVectorizationPlanner.h"
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#include "VPlanCFG.h"
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#include "llvm/Analysis/LoopIterator.h"
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#define DEBUG_TYPE "loop-vectorize"
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using namespace llvm;
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namespace {
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// Class that is used to build the plain CFG for the incoming IR.
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class PlainCFGBuilder {
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private:
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// The outermost loop of the input loop nest considered for vectorization.
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Loop *TheLoop;
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// Loop Info analysis.
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LoopInfo *LI;
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// Vectorization plan that we are working on.
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VPlan &Plan;
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// Builder of the VPlan instruction-level representation.
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VPBuilder VPIRBuilder;
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// NOTE: The following maps are intentionally destroyed after the plain CFG
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// construction because subsequent VPlan-to-VPlan transformation may
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// invalidate them.
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// Map incoming BasicBlocks to their newly-created VPBasicBlocks.
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DenseMap<BasicBlock *, VPBasicBlock *> BB2VPBB;
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// Map incoming Value definitions to their newly-created VPValues.
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DenseMap<Value *, VPValue *> IRDef2VPValue;
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// Hold phi node's that need to be fixed once the plain CFG has been built.
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SmallVector<PHINode *, 8> PhisToFix;
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/// Maps loops in the original IR to their corresponding region.
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DenseMap<Loop *, VPRegionBlock *> Loop2Region;
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// Utility functions.
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void setVPBBPredsFromBB(VPBasicBlock *VPBB, BasicBlock *BB);
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void setRegionPredsFromBB(VPRegionBlock *VPBB, BasicBlock *BB);
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void fixHeaderPhis();
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VPBasicBlock *getOrCreateVPBB(BasicBlock *BB);
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#ifndef NDEBUG
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bool isExternalDef(Value *Val);
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#endif
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VPValue *getOrCreateVPOperand(Value *IRVal);
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void createVPInstructionsForVPBB(VPBasicBlock *VPBB, BasicBlock *BB);
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public:
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PlainCFGBuilder(Loop *Lp, LoopInfo *LI, VPlan &P)
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: TheLoop(Lp), LI(LI), Plan(P) {}
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/// Build plain CFG for TheLoop and connects it to Plan's entry.
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void buildPlainCFG(DenseMap<VPBlockBase *, BasicBlock *> &VPB2IRBB);
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};
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} // anonymous namespace
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// Set predecessors of \p VPBB in the same order as they are in \p BB. \p VPBB
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// must have no predecessors.
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void PlainCFGBuilder::setVPBBPredsFromBB(VPBasicBlock *VPBB, BasicBlock *BB) {
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auto GetLatchOfExit = [this](BasicBlock *BB) -> BasicBlock * {
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auto *SinglePred = BB->getSinglePredecessor();
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Loop *LoopForBB = LI->getLoopFor(BB);
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if (!SinglePred || LI->getLoopFor(SinglePred) == LoopForBB)
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return nullptr;
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// The input IR must be in loop-simplify form, ensuring a single predecessor
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// for exit blocks.
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assert(SinglePred == LI->getLoopFor(SinglePred)->getLoopLatch() &&
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"SinglePred must be the only loop latch");
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return SinglePred;
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};
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if (auto *LatchBB = GetLatchOfExit(BB)) {
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auto *PredRegion = getOrCreateVPBB(LatchBB)->getParent();
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assert(VPBB == cast<VPBasicBlock>(PredRegion->getSingleSuccessor()) &&
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"successor must already be set for PredRegion; it must have VPBB "
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"as single successor");
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VPBB->setPredecessors({PredRegion});
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return;
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}
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// Collect VPBB predecessors.
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SmallVector<VPBlockBase *, 2> VPBBPreds;
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for (BasicBlock *Pred : predecessors(BB))
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VPBBPreds.push_back(getOrCreateVPBB(Pred));
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VPBB->setPredecessors(VPBBPreds);
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}
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static bool isHeaderBB(BasicBlock *BB, Loop *L) {
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return L && BB == L->getHeader();
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}
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void PlainCFGBuilder::setRegionPredsFromBB(VPRegionBlock *Region,
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BasicBlock *BB) {
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// BB is a loop header block. Connect the region to the loop preheader.
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Loop *LoopOfBB = LI->getLoopFor(BB);
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Region->setPredecessors({getOrCreateVPBB(LoopOfBB->getLoopPredecessor())});
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}
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// Add operands to VPInstructions representing phi nodes from the input IR.
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void PlainCFGBuilder::fixHeaderPhis() {
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for (auto *Phi : PhisToFix) {
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assert(IRDef2VPValue.count(Phi) && "Missing VPInstruction for PHINode.");
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VPValue *VPVal = IRDef2VPValue[Phi];
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assert(isa<VPWidenPHIRecipe>(VPVal) &&
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"Expected WidenPHIRecipe for phi node.");
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auto *VPPhi = cast<VPWidenPHIRecipe>(VPVal);
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assert(VPPhi->getNumOperands() == 0 &&
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"Expected VPInstruction with no operands.");
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Loop *L = LI->getLoopFor(Phi->getParent());
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assert(isHeaderBB(Phi->getParent(), L));
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// For header phis, make sure the incoming value from the loop
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// predecessor is the first operand of the recipe.
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assert(Phi->getNumOperands() == 2 &&
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"header phi must have exactly 2 operands");
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BasicBlock *LoopPred = L->getLoopPredecessor();
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VPPhi->addOperand(
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getOrCreateVPOperand(Phi->getIncomingValueForBlock(LoopPred)));
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BasicBlock *LoopLatch = L->getLoopLatch();
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VPPhi->addOperand(
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getOrCreateVPOperand(Phi->getIncomingValueForBlock(LoopLatch)));
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}
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}
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static bool isHeaderVPBB(VPBasicBlock *VPBB) {
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return VPBB->getParent() && VPBB->getParent()->getEntry() == VPBB;
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}
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/// Return true of \p L loop is contained within \p OuterLoop.
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static bool doesContainLoop(const Loop *L, const Loop *OuterLoop) {
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if (L->getLoopDepth() < OuterLoop->getLoopDepth())
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return false;
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const Loop *P = L;
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while (P) {
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if (P == OuterLoop)
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return true;
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P = P->getParentLoop();
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}
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return false;
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}
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// Create a new empty VPBasicBlock for an incoming BasicBlock in the region
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// corresponding to the containing loop or retrieve an existing one if it was
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// already created. If no region exists yet for the loop containing \p BB, a new
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// one is created.
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VPBasicBlock *PlainCFGBuilder::getOrCreateVPBB(BasicBlock *BB) {
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if (auto *VPBB = BB2VPBB.lookup(BB)) {
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// Retrieve existing VPBB.
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return VPBB;
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}
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// Create new VPBB.
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StringRef Name = isHeaderBB(BB, TheLoop) ? "vector.body" : BB->getName();
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LLVM_DEBUG(dbgs() << "Creating VPBasicBlock for " << Name << "\n");
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VPBasicBlock *VPBB = Plan.createVPBasicBlock(Name);
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BB2VPBB[BB] = VPBB;
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// Get or create a region for the loop containing BB, except for the top
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// region of TheLoop which is created later.
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Loop *LoopOfBB = LI->getLoopFor(BB);
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if (!LoopOfBB || LoopOfBB == TheLoop || !doesContainLoop(LoopOfBB, TheLoop))
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return VPBB;
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auto *RegionOfVPBB = Loop2Region.lookup(LoopOfBB);
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if (!isHeaderBB(BB, LoopOfBB)) {
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assert(RegionOfVPBB &&
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"Region should have been created by visiting header earlier");
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VPBB->setParent(RegionOfVPBB);
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return VPBB;
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}
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assert(!RegionOfVPBB &&
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"First visit of a header basic block expects to register its region.");
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// Handle a header - take care of its Region.
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RegionOfVPBB = Plan.createVPRegionBlock(Name.str(), false /*isReplicator*/);
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RegionOfVPBB->setParent(Loop2Region[LoopOfBB->getParentLoop()]);
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RegionOfVPBB->setEntry(VPBB);
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Loop2Region[LoopOfBB] = RegionOfVPBB;
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return VPBB;
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}
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#ifndef NDEBUG
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// Return true if \p Val is considered an external definition. An external
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// definition is either:
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// 1. A Value that is not an Instruction. This will be refined in the future.
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// 2. An Instruction that is outside of the CFG snippet represented in VPlan,
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// i.e., is not part of: a) the loop nest, b) outermost loop PH and, c)
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// outermost loop exits.
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bool PlainCFGBuilder::isExternalDef(Value *Val) {
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// All the Values that are not Instructions are considered external
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// definitions for now.
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Instruction *Inst = dyn_cast<Instruction>(Val);
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if (!Inst)
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return true;
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BasicBlock *InstParent = Inst->getParent();
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assert(InstParent && "Expected instruction parent.");
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// Check whether Instruction definition is in loop PH.
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BasicBlock *PH = TheLoop->getLoopPreheader();
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assert(PH && "Expected loop pre-header.");
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if (InstParent == PH)
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// Instruction definition is in outermost loop PH.
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return false;
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// Check whether Instruction definition is in a loop exit.
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SmallVector<BasicBlock *> ExitBlocks;
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TheLoop->getExitBlocks(ExitBlocks);
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if (is_contained(ExitBlocks, InstParent)) {
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// Instruction definition is in outermost loop exit.
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return false;
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}
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// Check whether Instruction definition is in loop body.
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return !TheLoop->contains(Inst);
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}
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#endif
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// Create a new VPValue or retrieve an existing one for the Instruction's
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// operand \p IRVal. This function must only be used to create/retrieve VPValues
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// for *Instruction's operands* and not to create regular VPInstruction's. For
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// the latter, please, look at 'createVPInstructionsForVPBB'.
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VPValue *PlainCFGBuilder::getOrCreateVPOperand(Value *IRVal) {
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auto VPValIt = IRDef2VPValue.find(IRVal);
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if (VPValIt != IRDef2VPValue.end())
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// Operand has an associated VPInstruction or VPValue that was previously
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// created.
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return VPValIt->second;
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// Operand doesn't have a previously created VPInstruction/VPValue. This
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// means that operand is:
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// A) a definition external to VPlan,
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// B) any other Value without specific representation in VPlan.
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// For now, we use VPValue to represent A and B and classify both as external
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// definitions. We may introduce specific VPValue subclasses for them in the
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// future.
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assert(isExternalDef(IRVal) && "Expected external definition as operand.");
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// A and B: Create VPValue and add it to the pool of external definitions and
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// to the Value->VPValue map.
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VPValue *NewVPVal = Plan.getOrAddLiveIn(IRVal);
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IRDef2VPValue[IRVal] = NewVPVal;
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return NewVPVal;
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}
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// Create new VPInstructions in a VPBasicBlock, given its BasicBlock
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// counterpart. This function must be invoked in RPO so that the operands of a
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// VPInstruction in \p BB have been visited before (except for Phi nodes).
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void PlainCFGBuilder::createVPInstructionsForVPBB(VPBasicBlock *VPBB,
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BasicBlock *BB) {
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VPIRBuilder.setInsertPoint(VPBB);
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// TODO: Model and preserve debug intrinsics in VPlan.
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for (Instruction &InstRef : BB->instructionsWithoutDebug(false)) {
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Instruction *Inst = &InstRef;
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// There shouldn't be any VPValue for Inst at this point. Otherwise, we
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// visited Inst when we shouldn't, breaking the RPO traversal order.
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assert(!IRDef2VPValue.count(Inst) &&
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"Instruction shouldn't have been visited.");
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if (auto *Br = dyn_cast<BranchInst>(Inst)) {
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if (TheLoop->getLoopLatch() == BB ||
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any_of(successors(BB),
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[this](BasicBlock *Succ) { return !TheLoop->contains(Succ); }))
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continue;
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// Conditional branch instruction are represented using BranchOnCond
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// recipes.
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if (Br->isConditional()) {
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VPValue *Cond = getOrCreateVPOperand(Br->getCondition());
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VPIRBuilder.createNaryOp(VPInstruction::BranchOnCond, {Cond}, Inst);
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}
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// Skip the rest of the Instruction processing for Branch instructions.
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continue;
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}
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if (auto *SI = dyn_cast<SwitchInst>(Inst)) {
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SmallVector<VPValue *> Ops = {getOrCreateVPOperand(SI->getCondition())};
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for (auto Case : SI->cases())
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Ops.push_back(getOrCreateVPOperand(Case.getCaseValue()));
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VPIRBuilder.createNaryOp(Instruction::Switch, Ops, Inst);
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continue;
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}
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VPSingleDefRecipe *NewR;
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if (auto *Phi = dyn_cast<PHINode>(Inst)) {
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// Phi node's operands may have not been visited at this point. We create
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// an empty VPInstruction that we will fix once the whole plain CFG has
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// been built.
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NewR = new VPWidenPHIRecipe(Phi, nullptr, Phi->getDebugLoc(), "vec.phi");
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VPBB->appendRecipe(NewR);
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if (isHeaderBB(Phi->getParent(), LI->getLoopFor(Phi->getParent()))) {
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// Header phis need to be fixed after the VPBB for the latch has been
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// created.
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PhisToFix.push_back(Phi);
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} else {
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// Add operands for VPPhi in the order matching its predecessors in
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// VPlan.
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DenseMap<const VPBasicBlock *, VPValue *> VPPredToIncomingValue;
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for (unsigned I = 0; I != Phi->getNumOperands(); ++I) {
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VPPredToIncomingValue[BB2VPBB[Phi->getIncomingBlock(I)]] =
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getOrCreateVPOperand(Phi->getIncomingValue(I));
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}
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for (VPBlockBase *Pred : VPBB->getPredecessors())
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NewR->addOperand(
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VPPredToIncomingValue.lookup(Pred->getExitingBasicBlock()));
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}
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} else {
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// Translate LLVM-IR operands into VPValue operands and set them in the
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// new VPInstruction.
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SmallVector<VPValue *, 4> VPOperands;
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for (Value *Op : Inst->operands())
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VPOperands.push_back(getOrCreateVPOperand(Op));
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// Build VPInstruction for any arbitrary Instruction without specific
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// representation in VPlan.
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NewR = cast<VPInstruction>(
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VPIRBuilder.createNaryOp(Inst->getOpcode(), VPOperands, Inst));
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}
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IRDef2VPValue[Inst] = NewR;
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}
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}
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// Main interface to build the plain CFG.
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void PlainCFGBuilder::buildPlainCFG(
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DenseMap<VPBlockBase *, BasicBlock *> &VPB2IRBB) {
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// 1. Scan the body of the loop in a topological order to visit each basic
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// block after having visited its predecessor basic blocks. Create a VPBB for
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// each BB and link it to its successor and predecessor VPBBs. Note that
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// predecessors must be set in the same order as they are in the incomming IR.
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// Otherwise, there might be problems with existing phi nodes and algorithm
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// based on predecessors traversal.
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// Loop PH needs to be explicitly visited since it's not taken into account by
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// LoopBlocksDFS.
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BasicBlock *ThePreheaderBB = TheLoop->getLoopPreheader();
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assert((ThePreheaderBB->getTerminator()->getNumSuccessors() == 1) &&
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"Unexpected loop preheader");
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for (auto &I : *ThePreheaderBB) {
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if (I.getType()->isVoidTy())
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continue;
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IRDef2VPValue[&I] = Plan.getOrAddLiveIn(&I);
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}
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LoopBlocksRPO RPO(TheLoop);
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RPO.perform(LI);
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for (BasicBlock *BB : RPO) {
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// Create or retrieve the VPBasicBlock for this BB.
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VPBasicBlock *VPBB = getOrCreateVPBB(BB);
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VPRegionBlock *Region = VPBB->getParent();
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Loop *LoopForBB = LI->getLoopFor(BB);
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// Set VPBB predecessors in the same order as they are in the incoming BB.
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if (!isHeaderBB(BB, LoopForBB)) {
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setVPBBPredsFromBB(VPBB, BB);
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} else if (Region) {
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// BB is a loop header and there's a corresponding region, set the
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// predecessor for it.
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setRegionPredsFromBB(Region, BB);
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}
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// Create VPInstructions for BB.
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createVPInstructionsForVPBB(VPBB, BB);
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if (BB == TheLoop->getLoopLatch()) {
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VPBasicBlock *HeaderVPBB = getOrCreateVPBB(LoopForBB->getHeader());
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VPBlockUtils::connectBlocks(VPBB, HeaderVPBB);
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continue;
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}
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// Set VPBB successors. We create empty VPBBs for successors if they don't
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// exist already. Recipes will be created when the successor is visited
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// during the RPO traversal.
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if (auto *SI = dyn_cast<SwitchInst>(BB->getTerminator())) {
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SmallVector<VPBlockBase *> Succs = {
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getOrCreateVPBB(SI->getDefaultDest())};
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for (auto Case : SI->cases())
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Succs.push_back(getOrCreateVPBB(Case.getCaseSuccessor()));
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VPBB->setSuccessors(Succs);
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continue;
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}
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auto *BI = cast<BranchInst>(BB->getTerminator());
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unsigned NumSuccs = succ_size(BB);
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if (NumSuccs == 1) {
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auto *Successor = getOrCreateVPBB(BB->getSingleSuccessor());
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VPBB->setOneSuccessor(isHeaderVPBB(Successor)
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? Successor->getParent()
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: static_cast<VPBlockBase *>(Successor));
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continue;
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}
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assert(BI->isConditional() && NumSuccs == 2 && BI->isConditional() &&
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"block must have conditional branch with 2 successors");
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BasicBlock *IRSucc0 = BI->getSuccessor(0);
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BasicBlock *IRSucc1 = BI->getSuccessor(1);
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VPBasicBlock *Successor0 = getOrCreateVPBB(IRSucc0);
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VPBasicBlock *Successor1 = getOrCreateVPBB(IRSucc1);
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if (BB == LoopForBB->getLoopLatch()) {
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// For a latch we need to set the successor of the region rather than that
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// of VPBB and it should be set to the exit, i.e., non-header successor,
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// except for the top region, which is handled elsewhere.
|
|
assert(LoopForBB != TheLoop &&
|
|
"Latch of the top region should have been handled earlier");
|
|
Region->setOneSuccessor(isHeaderVPBB(Successor0) ? Successor1
|
|
: Successor0);
|
|
Region->setExiting(VPBB);
|
|
continue;
|
|
}
|
|
|
|
// Don't connect any blocks outside the current loop except the latch for
|
|
// now. The latch is handled above.
|
|
if (LoopForBB) {
|
|
if (!LoopForBB->contains(IRSucc0)) {
|
|
VPBB->setOneSuccessor(Successor1);
|
|
continue;
|
|
}
|
|
if (!LoopForBB->contains(IRSucc1)) {
|
|
VPBB->setOneSuccessor(Successor0);
|
|
continue;
|
|
}
|
|
}
|
|
|
|
VPBB->setTwoSuccessors(Successor0, Successor1);
|
|
}
|
|
|
|
// 2. The whole CFG has been built at this point so all the input Values must
|
|
// have a VPlan counterpart. Fix VPlan header phi by adding their
|
|
// corresponding VPlan operands.
|
|
fixHeaderPhis();
|
|
|
|
VPBlockUtils::connectBlocks(Plan.getEntry(),
|
|
getOrCreateVPBB(TheLoop->getHeader()));
|
|
|
|
for (const auto &[IRBB, VPB] : BB2VPBB)
|
|
VPB2IRBB[VPB] = IRBB;
|
|
}
|
|
|
|
void VPlanHCFGBuilder::buildPlainCFG() {
|
|
PlainCFGBuilder PCFGBuilder(TheLoop, LI, Plan);
|
|
PCFGBuilder.buildPlainCFG(VPB2IRBB);
|
|
}
|
|
|
|
// Public interface to build a H-CFG.
|
|
void VPlanHCFGBuilder::buildHierarchicalCFG() {
|
|
// Build Top Region enclosing the plain CFG.
|
|
buildPlainCFG();
|
|
LLVM_DEBUG(Plan.setName("HCFGBuilder: Plain CFG\n"); dbgs() << Plan);
|
|
}
|