fc0653f31c
Recent upstream trends have moved away from explicitly using `-verify-machineinstrs`, as it's already covered by the expensive checks. This PR removes almost all `-verify-machineinstrs` from tests in `llvm/test/CodeGen/AMDGPU/*.ll`, leaving only those tests where its removal currently causes failures.
83 lines
3.5 KiB
LLVM
83 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GPRIDX %s
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,MOVREL %s
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
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define void @main(<19 x i32> %arg) {
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; GCN-LABEL: main:
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: s_mov_b32 s4, 0
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; GCN-NEXT: s_mov_b32 s12, s4
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; GCN-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0
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; GCN-NEXT: v_mov_b32_e32 v1, 0
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; GCN-NEXT: s_mov_b32 s13, s4
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; GCN-NEXT: v_mov_b32_e32 v4, s12
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; GCN-NEXT: s_mov_b32 s5, s4
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; GCN-NEXT: s_mov_b32 s6, s4
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; GCN-NEXT: s_mov_b32 s7, s4
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; GCN-NEXT: s_mov_b32 s8, s4
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; GCN-NEXT: s_mov_b32 s9, s4
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; GCN-NEXT: s_mov_b32 s10, s4
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; GCN-NEXT: s_mov_b32 s11, s4
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; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
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; GCN-NEXT: v_mov_b32_e32 v2, v1
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; GCN-NEXT: v_mov_b32_e32 v3, v1
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; GCN-NEXT: v_mov_b32_e32 v5, s13
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; GCN-NEXT: image_store v[0:3], v[4:5], s[4:11] unorm
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10-LABEL: main:
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; GFX10: ; %bb.0: ; %bb
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: v_mov_b32_e32 v1, 0
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; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0
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; GFX10-NEXT: s_mov_b32 s4, 0
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; GFX10-NEXT: s_mov_b32 s5, s4
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; GFX10-NEXT: v_mov_b32_e32 v2, v1
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; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
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; GFX10-NEXT: v_mov_b32_e32 v3, v1
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; GFX10-NEXT: s_mov_b32 s6, s4
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; GFX10-NEXT: s_mov_b32 s7, s4
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; GFX10-NEXT: s_mov_b32 s8, s4
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; GFX10-NEXT: s_mov_b32 s9, s4
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; GFX10-NEXT: s_mov_b32 s10, s4
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; GFX10-NEXT: s_mov_b32 s11, s4
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; GFX10-NEXT: image_store v[0:3], [v1, v1], s[4:11] dim:SQ_RSRC_IMG_2D unorm
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-LABEL: main:
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; GFX11: ; %bb.0: ; %bb
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_mov_b32_e32 v1, 0
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; GFX11-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0
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; GFX11-NEXT: s_mov_b32 s0, 0
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; GFX11-NEXT: s_mov_b32 s1, s0
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; GFX11-NEXT: v_mov_b32_e32 v2, v1
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; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
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; GFX11-NEXT: v_mov_b32_e32 v3, v1
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; GFX11-NEXT: s_mov_b32 s2, s0
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; GFX11-NEXT: s_mov_b32 s3, s0
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; GFX11-NEXT: s_mov_b32 s4, s0
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; GFX11-NEXT: s_mov_b32 s5, s0
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; GFX11-NEXT: s_mov_b32 s6, s0
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; GFX11-NEXT: s_mov_b32 s7, s0
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; GFX11-NEXT: image_store v[0:3], [v1, v1], s[0:7] dim:SQ_RSRC_IMG_2D unorm
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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bb:
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%i = bitcast <19 x i32> %arg to <38 x i16>
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%i1 = extractelement <38 x i16> %i, i64 0
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%i2 = icmp eq i16 %i1, 0
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%i3 = zext i1 %i2 to i32
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%i4 = bitcast i32 %i3 to float
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%i5 = insertelement <4 x float> zeroinitializer, float %i4, i64 0
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call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %i5, i32 0, i32 0, i32 0, <8 x i32> zeroinitializer, i32 0, i32 0)
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ret void
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}
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declare void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float>, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg)
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; GFX10PLUS: {{.*}}
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; GPRIDX: {{.*}}
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; MOVREL: {{.*}}
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