4e63e0457c
Canonicalize it to a G_AND instead so that ISel patterns can pick it up and ignore it, as the shift instructions only read low bits. G_ZEXT would be lowered to a v/s_and anyway in most cases. I'm also looking at making a DAG version of this in a separate patch.
147 lines
4.6 KiB
YAML
147 lines
4.6 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn -run-pass=amdgpu-regbank-combiner %s -o - | FileCheck %s
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---
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name: lshr_zext_i16
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; CHECK-LABEL: name: lshr_zext_i16
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; CHECK: liveins: $sgpr0, $sgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %src:sgpr(s32) = COPY $sgpr0
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; CHECK-NEXT: %regamt:sgpr(s32) = COPY $sgpr1
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 65535
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; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND %regamt, [[C]]
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; CHECK-NEXT: %res:sgpr(s32) = G_LSHR %src, [[AND]](s32)
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; CHECK-NEXT: $sgpr0 = COPY %res(s32)
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%src:sgpr(s32) = COPY $sgpr0
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%regamt:sgpr(s32) = COPY $sgpr1
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%amt:sgpr(s16) = G_TRUNC %regamt
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%zextamt:sgpr(s32) = G_ZEXT %amt
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%res:sgpr(s32) = G_LSHR %src, %zextamt
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$sgpr0 = COPY %res
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...
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---
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name: ashr_zext_i16
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; CHECK-LABEL: name: ashr_zext_i16
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; CHECK: liveins: $sgpr0, $sgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %src:sgpr(s32) = COPY $sgpr0
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; CHECK-NEXT: %regamt:sgpr(s32) = COPY $sgpr1
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 65535
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; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND %regamt, [[C]]
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; CHECK-NEXT: %res:sgpr(s32) = G_ASHR %src, [[AND]](s32)
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; CHECK-NEXT: $sgpr0 = COPY %res(s32)
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%src:sgpr(s32) = COPY $sgpr0
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%regamt:sgpr(s32) = COPY $sgpr1
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%amt:sgpr(s16) = G_TRUNC %regamt
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%zextamt:sgpr(s32) = G_ZEXT %amt
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%res:sgpr(s32) = G_ASHR %src, %zextamt
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$sgpr0 = COPY %res
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...
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---
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name: shl_zext_i16
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; CHECK-LABEL: name: shl_zext_i16
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; CHECK: liveins: $sgpr0, $sgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %src:sgpr(s32) = COPY $sgpr0
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; CHECK-NEXT: %regamt:sgpr(s32) = COPY $sgpr1
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 65535
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; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND %regamt, [[C]]
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; CHECK-NEXT: %res:sgpr(s32) = G_SHL %src, [[AND]](s32)
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; CHECK-NEXT: $sgpr0 = COPY %res(s32)
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%src:sgpr(s32) = COPY $sgpr0
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%regamt:sgpr(s32) = COPY $sgpr1
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%amt:sgpr(s16) = G_TRUNC %regamt
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%zextamt:sgpr(s32) = G_ZEXT %amt
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%res:sgpr(s32) = G_SHL %src, %zextamt
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$sgpr0 = COPY %res
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...
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---
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name: lshr_zext_i8
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; CHECK-LABEL: name: lshr_zext_i8
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; CHECK: liveins: $sgpr0, $sgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %src:sgpr(s32) = COPY $sgpr0
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; CHECK-NEXT: %regamt:sgpr(s32) = COPY $sgpr1
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 255
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; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND %regamt, [[C]]
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; CHECK-NEXT: %res:sgpr(s32) = G_LSHR %src, [[AND]](s32)
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; CHECK-NEXT: $sgpr0 = COPY %res(s32)
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%src:sgpr(s32) = COPY $sgpr0
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%regamt:sgpr(s32) = COPY $sgpr1
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%amt:sgpr(s8) = G_TRUNC %regamt
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%zextamt:sgpr(s32) = G_ZEXT %amt
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%res:sgpr(s32) = G_LSHR %src, %zextamt
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$sgpr0 = COPY %res
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...
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---
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name: ashr_zext_i8
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; CHECK-LABEL: name: ashr_zext_i8
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; CHECK: liveins: $sgpr0, $sgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %src:sgpr(s32) = COPY $sgpr0
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; CHECK-NEXT: %regamt:sgpr(s32) = COPY $sgpr1
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 255
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; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND %regamt, [[C]]
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; CHECK-NEXT: %res:sgpr(s32) = G_ASHR %src, [[AND]](s32)
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; CHECK-NEXT: $sgpr0 = COPY %res(s32)
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%src:sgpr(s32) = COPY $sgpr0
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%regamt:sgpr(s32) = COPY $sgpr1
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%amt:sgpr(s8) = G_TRUNC %regamt
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%zextamt:sgpr(s32) = G_ZEXT %amt
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%res:sgpr(s32) = G_ASHR %src, %zextamt
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$sgpr0 = COPY %res
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...
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---
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name: shl_zext_i8
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; CHECK-LABEL: name: shl_zext_i8
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; CHECK: liveins: $sgpr0, $sgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %src:sgpr(s32) = COPY $sgpr0
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; CHECK-NEXT: %regamt:sgpr(s32) = COPY $sgpr1
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 255
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; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND %regamt, [[C]]
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; CHECK-NEXT: %res:sgpr(s32) = G_SHL %src, [[AND]](s32)
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; CHECK-NEXT: $sgpr0 = COPY %res(s32)
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%src:sgpr(s32) = COPY $sgpr0
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%regamt:sgpr(s32) = COPY $sgpr1
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%amt:sgpr(s8) = G_TRUNC %regamt
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%zextamt:sgpr(s32) = G_ZEXT %amt
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%res:sgpr(s32) = G_SHL %src, %zextamt
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$sgpr0 = COPY %res
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...
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