9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
127 lines
4.6 KiB
YAML
127 lines
4.6 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=SI %s
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# RUN: FileCheck -check-prefix=ERR %s < %t
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# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX9 %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX9 %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX9 %s
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# ERR-NOT: remark:
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# ERR: remark: <unknown>:0:0: cannot select: %2:sgpr(s32) = G_SMULH %0:sgpr, %1:sgpr (in function: smulh_s32_ss)
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# ERR-NOT: remark:
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---
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name: smulh_s32_ss
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; SI-LABEL: name: smulh_s32_ss
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; SI: liveins: $sgpr0, $sgpr1
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; SI-NEXT: {{ $}}
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; SI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; SI-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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; SI-NEXT: [[SMULH:%[0-9]+]]:sgpr(s32) = G_SMULH [[COPY]], [[COPY1]]
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; SI-NEXT: S_ENDPGM 0, implicit [[SMULH]](s32)
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; GFX9-LABEL: name: smulh_s32_ss
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; GFX9: liveins: $sgpr0, $sgpr1
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; GFX9-NEXT: {{ $}}
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; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GFX9-NEXT: [[S_MUL_HI_I32_:%[0-9]+]]:sreg_32 = S_MUL_HI_I32 [[COPY]], [[COPY1]]
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; GFX9-NEXT: S_ENDPGM 0, implicit [[S_MUL_HI_I32_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = COPY $sgpr1
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%2:sgpr(s32) = G_SMULH %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: smulh_s32_sv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; SI-LABEL: name: smulh_s32_sv
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; SI: liveins: $sgpr0, $vgpr0
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; SI-NEXT: {{ $}}
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; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; SI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; SI-NEXT: [[V_MUL_HI_I32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_HI_I32_e64 [[COPY]], [[COPY1]], implicit $exec
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; SI-NEXT: S_ENDPGM 0, implicit [[V_MUL_HI_I32_e64_]]
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; GFX9-LABEL: name: smulh_s32_sv
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; GFX9: liveins: $sgpr0, $vgpr0
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; GFX9-NEXT: {{ $}}
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; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX9-NEXT: [[V_MUL_HI_I32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_HI_I32_e64 [[COPY]], [[COPY1]], implicit $exec
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; GFX9-NEXT: S_ENDPGM 0, implicit [[V_MUL_HI_I32_e64_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = COPY $vgpr0
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%2:vgpr(s32) = G_SMULH %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: smulh_s32_vs
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; SI-LABEL: name: smulh_s32_vs
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; SI: liveins: $sgpr0, $vgpr0
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; SI-NEXT: {{ $}}
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; SI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; SI-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; SI-NEXT: [[V_MUL_HI_I32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_HI_I32_e64 [[COPY]], [[COPY1]], implicit $exec
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; SI-NEXT: S_ENDPGM 0, implicit [[V_MUL_HI_I32_e64_]]
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; GFX9-LABEL: name: smulh_s32_vs
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; GFX9: liveins: $sgpr0, $vgpr0
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; GFX9-NEXT: {{ $}}
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; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX9-NEXT: [[V_MUL_HI_I32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_HI_I32_e64 [[COPY]], [[COPY1]], implicit $exec
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; GFX9-NEXT: S_ENDPGM 0, implicit [[V_MUL_HI_I32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr(s32) = COPY $sgpr0
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%2:vgpr(s32) = G_SMULH %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: smulh_s32_vv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; SI-LABEL: name: smulh_s32_vv
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; SI: liveins: $vgpr0, $vgpr1
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; SI-NEXT: {{ $}}
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; SI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; SI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; SI-NEXT: [[V_MUL_HI_I32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_HI_I32_e64 [[COPY]], [[COPY1]], implicit $exec
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; SI-NEXT: S_ENDPGM 0, implicit [[V_MUL_HI_I32_e64_]]
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; GFX9-LABEL: name: smulh_s32_vv
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; GFX9: liveins: $vgpr0, $vgpr1
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; GFX9-NEXT: {{ $}}
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; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX9-NEXT: [[V_MUL_HI_I32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_HI_I32_e64 [[COPY]], [[COPY1]], implicit $exec
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; GFX9-NEXT: S_ENDPGM 0, implicit [[V_MUL_HI_I32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s32) = G_SMULH %0, %1
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S_ENDPGM 0, implicit %2
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...
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