fc0653f31c
Recent upstream trends have moved away from explicitly using `-verify-machineinstrs`, as it's already covered by the expensive checks. This PR removes almost all `-verify-machineinstrs` from tests in `llvm/test/CodeGen/AMDGPU/*.ll`, leaving only those tests where its removal currently causes failures.
38 lines
1.2 KiB
LLVM
38 lines
1.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s
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define amdgpu_kernel void @test_wave64(i32 %arg0, i64 %saved) {
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; GCN-LABEL: test_wave64:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_load_dword s0, s[8:9], 0x0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_cmp_lg_u32 s0, 0
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; GCN-NEXT: s_cbranch_scc1 .LBB0_2
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; GCN-NEXT: ; %bb.1: ; %mid
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; GCN-NEXT: v_mov_b32_e32 v0, 0
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; GCN-NEXT: global_store_dword v[0:1], v0, off
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: .LBB0_2: ; %bb
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x8
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_or_b64 exec, exec, s[0:1]
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; GCN-NEXT: v_mov_b32_e32 v0, 0
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; GCN-NEXT: global_store_dword v[0:1], v0, off
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: s_endpgm
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entry:
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%cond = icmp eq i32 %arg0, 0
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br i1 %cond, label %mid, label %bb
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mid:
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store volatile i32 0, ptr addrspace(1) poison
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br label %bb
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bb:
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call void @llvm.amdgcn.end.cf.i64(i64 %saved)
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store volatile i32 0, ptr addrspace(1) poison
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ret void
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}
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declare void @llvm.amdgcn.end.cf.i64(i64 %val)
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