e8e816344e
In some cases this will require an avoidable re-defining of a register, but it works out better most of the time. Also allow folding 64-bit immediates into subregister extracts, unless it would break an inline constant. We could be more aggressive here, but this set of conditions seems to do a reasonable job without introducing too many regressions.
187 lines
7.7 KiB
LLVM
187 lines
7.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a %s -o - | FileCheck %s
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declare ptr @G()
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define amdgpu_kernel void @foo(ptr addrspace(5) %ptr5, ptr %p0, double %v0, <4 x i32> %vec) {
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; CHECK-LABEL: foo:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_add_u32 flat_scratch_lo, s12, s17
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; CHECK-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
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; CHECK-NEXT: v_pk_mov_b32 v[46:47], 0, 0
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; CHECK-NEXT: flat_load_dword v42, v[46:47]
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; CHECK-NEXT: s_mov_b64 s[38:39], s[6:7]
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; CHECK-NEXT: s_mov_b64 s[48:49], s[4:5]
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; CHECK-NEXT: s_load_dwordx4 s[4:7], s[8:9], 0x8
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; CHECK-NEXT: s_load_dword s64, s[8:9], 0x0
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; CHECK-NEXT: s_add_u32 s0, s0, s17
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; CHECK-NEXT: s_addc_u32 s1, s1, 0
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; CHECK-NEXT: s_mov_b64 s[34:35], s[8:9]
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_accvgpr_write_b32 a32, s6
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; CHECK-NEXT: v_accvgpr_write_b32 a33, s7
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; CHECK-NEXT: s_mov_b64 s[6:7], src_private_base
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; CHECK-NEXT: s_cmp_lg_u32 s64, -1
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; CHECK-NEXT: s_cselect_b32 s7, s7, 0
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; CHECK-NEXT: s_cselect_b32 s8, s64, 0
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; CHECK-NEXT: s_add_u32 s50, s34, 48
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; CHECK-NEXT: s_addc_u32 s51, s35, 0
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; CHECK-NEXT: v_pk_mov_b32 v[58:59], s[4:5], s[4:5] op_sel:[0,1]
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; CHECK-NEXT: s_getpc_b64 s[4:5]
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; CHECK-NEXT: s_add_u32 s4, s4, G@gotpcrel32@lo+4
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; CHECK-NEXT: s_addc_u32 s5, s5, G@gotpcrel32@hi+12
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; CHECK-NEXT: s_load_dwordx2 s[54:55], s[4:5], 0x0
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; CHECK-NEXT: s_mov_b32 s6, 0
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; CHECK-NEXT: v_mov_b32_e32 v57, s7
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; CHECK-NEXT: s_mov_b32 s7, s6
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; CHECK-NEXT: s_mov_b32 s53, s14
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; CHECK-NEXT: v_mov_b32_e32 v56, s8
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; CHECK-NEXT: v_pk_mov_b32 v[60:61], s[6:7], s[6:7] op_sel:[0,1]
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; CHECK-NEXT: s_mov_b64 s[4:5], s[48:49]
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; CHECK-NEXT: s_mov_b64 s[6:7], s[38:39]
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; CHECK-NEXT: s_mov_b64 s[8:9], s[50:51]
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; CHECK-NEXT: s_mov_b32 s12, s14
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; CHECK-NEXT: s_mov_b32 s13, s15
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; CHECK-NEXT: s_mov_b32 s14, s16
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; CHECK-NEXT: v_mov_b32_e32 v31, v0
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; CHECK-NEXT: s_mov_b32 s32, 0
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; CHECK-NEXT: s_mov_b32 s33, s16
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; CHECK-NEXT: s_mov_b32 s52, s15
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; CHECK-NEXT: s_mov_b64 s[36:37], s[10:11]
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; CHECK-NEXT: v_mov_b32_e32 v40, v0
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; CHECK-NEXT: flat_store_dwordx2 v[58:59], v[60:61]
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; CHECK-NEXT: ; kill: def $sgpr15 killed $sgpr15
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_swappc_b64 s[30:31], s[54:55]
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; CHECK-NEXT: flat_load_dwordx2 v[62:63], v[58:59]
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; CHECK-NEXT: v_mov_b32_e32 v44, 0
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; CHECK-NEXT: v_mov_b32_e32 v45, 0x3ff00000
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; CHECK-NEXT: s_mov_b64 s[4:5], s[48:49]
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; CHECK-NEXT: s_mov_b64 s[6:7], s[38:39]
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; CHECK-NEXT: s_mov_b64 s[8:9], s[50:51]
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; CHECK-NEXT: s_mov_b64 s[10:11], s[36:37]
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; CHECK-NEXT: s_mov_b32 s12, s53
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; CHECK-NEXT: s_mov_b32 s13, s52
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; CHECK-NEXT: s_mov_b32 s14, s33
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; CHECK-NEXT: v_mov_b32_e32 v31, v40
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; CHECK-NEXT: flat_store_dwordx2 v[46:47], v[44:45]
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; CHECK-NEXT: flat_store_dwordx2 v[58:59], v[60:61]
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: ; kill: def $sgpr15 killed $sgpr15
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; CHECK-NEXT: s_swappc_b64 s[30:31], s[54:55]
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; CHECK-NEXT: flat_load_dwordx2 v[0:1], v[56:57] glc
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; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v0, s64
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; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 0, v42
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; CHECK-NEXT: flat_store_dwordx2 v[58:59], v[62:63]
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: flat_store_dwordx2 v[58:59], a[32:33]
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; CHECK-NEXT: buffer_store_dword a33, v0, s[0:3], 0 offen offset:4
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; CHECK-NEXT: buffer_store_dword v44, v0, s[0:3], 0 offen
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; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
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; CHECK-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
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; CHECK-NEXT: s_cbranch_execz .LBB0_4
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; CHECK-NEXT: ; %bb.1: ; %LeafBlock5
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; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 1, v42
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; CHECK-NEXT: s_and_saveexec_b64 s[6:7], vcc
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; CHECK-NEXT: ; %bb.2: ; %sw.bb17.i.i.i.i
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; CHECK-NEXT: v_mov_b32_e32 v44, 1
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; CHECK-NEXT: ; %bb.3: ; %Flow
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; CHECK-NEXT: s_or_b64 exec, exec, s[6:7]
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; CHECK-NEXT: .LBB0_4: ; %Flow8
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; CHECK-NEXT: s_or_saveexec_b64 s[4:5], s[4:5]
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; CHECK-NEXT: v_pk_mov_b32 v[0:1], v[42:43], v[42:43] op_sel:[0,1]
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; CHECK-NEXT: v_pk_mov_b32 v[2:3], v[44:45], v[44:45] op_sel:[0,1]
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; CHECK-NEXT: s_xor_b64 exec, exec, s[4:5]
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; CHECK-NEXT: s_cbranch_execz .LBB0_8
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; CHECK-NEXT: ; %bb.5: ; %LeafBlock
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; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v42
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; CHECK-NEXT: v_pk_mov_b32 v[0:1], v[42:43], v[42:43] op_sel:[0,1]
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; CHECK-NEXT: v_pk_mov_b32 v[2:3], v[44:45], v[44:45] op_sel:[0,1]
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; CHECK-NEXT: s_and_saveexec_b64 s[6:7], vcc
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; CHECK-NEXT: ; %bb.6: ; %sw.bb.i.i.i.i
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: ; %bb.7: ; %Flow7
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; CHECK-NEXT: s_or_b64 exec, exec, s[6:7]
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; CHECK-NEXT: v_mov_b32_e32 v44, 0
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; CHECK-NEXT: .LBB0_8: ; %bb.1
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; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
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; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v44
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; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
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; CHECK-NEXT: s_cbranch_execz .LBB0_10
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; CHECK-NEXT: ; %bb.9: ; %sw.bb.i.i.i.i.i
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; CHECK-NEXT: s_load_dwordx4 s[8:11], s[34:35], 0x20
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_pk_mov_b32 v[0:1], s[8:9], s[8:9] op_sel:[0,1]
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; CHECK-NEXT: v_pk_mov_b32 v[2:3], s[10:11], s[10:11] op_sel:[0,1]
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; CHECK-NEXT: .LBB0_10: ; %bb.2
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; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
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; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
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; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
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; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
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; CHECK-NEXT: buffer_store_dword v42, off, s[0:3], 0
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; CHECK-NEXT: s_endpgm
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entry:
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%load.null = load i32, ptr null, align 8
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%insert = insertelement <4 x i32> zeroinitializer, i32 %load.null, i64 0
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%cast = addrspacecast ptr addrspace(5) %ptr5 to ptr
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store double 0.000000e+00, ptr %p0, align 8
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%call = tail call ptr @G()
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store double 1.000000e+00, ptr null, align 8
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%load.0 = load double, ptr %p0, align 8
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store volatile double 0.000000e+00, ptr %p0, align 8
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%call.1 = tail call ptr @G()
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%load.1 = load volatile double, ptr %cast, align 8
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store volatile double %load.0, ptr %p0, align 8
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store double %v0, ptr %p0, align 8
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%load.2 = load double, ptr %p0, align 8
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store double %load.2, ptr addrspace(5) %ptr5, align 8
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store i32 0, ptr addrspace(5) %ptr5, align 4
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switch i32 %load.null, label %bb.1 [
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i32 0, label %sw.bb.i.i.i.i
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i32 1, label %sw.bb17.i.i.i.i
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]
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sw.bb.i.i.i.i: ; preds = %entry
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br label %bb.1
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sw.bb17.i.i.i.i: ; preds = %entry
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br label %bb.1
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bb.1: ; preds = %sw.bb17.i.i.i.i, %sw.bb.i.i.i.i, %entry
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%phi.0 = phi i32 [ 0, %entry ], [ 0, %sw.bb.i.i.i.i ], [ 1, %sw.bb17.i.i.i.i ]
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%phi.1 = phi <4 x i32> [ %insert, %entry ], [ zeroinitializer, %sw.bb.i.i.i.i ], [ %insert, %sw.bb17.i.i.i.i ]
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switch i32 %phi.0, label %bb.2 [
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i32 0, label %sw.bb.i.i.i.i.i
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]
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sw.bb.i.i.i.i.i: ; preds = %bb.1
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br label %bb.2
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bb.2: ; preds = %sw.bb.i.i.i.i.i, %bb.1
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%phi.2 = phi <4 x i32> [ %phi.1, %bb.1 ], [ %vec, %sw.bb.i.i.i.i.i ]
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%extract.1 = extractelement <4 x i32> %phi.2, i64 0
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switch i32 1, label %bb.3 [
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i32 0, label %sw.bb.i.i5.i.i
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]
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sw.bb.i.i5.i.i: ; preds = %bb.2
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br label %bb.3
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bb.3: ; preds = %sw.bb.i.i5.i.i, %bb.2
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%phi.3 = phi <4 x i32> [ zeroinitializer, %sw.bb.i.i5.i.i ], [ %insert, %bb.2 ]
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switch i32 %extract.1, label %bb.4 [
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i32 0, label %sw.bb7.i.i.i3.i.i
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]
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sw.bb7.i.i.i3.i.i: ; preds = %bb.3
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%insert.0 = insertelement <4 x i32> %insert, i32 0, i64 1
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br label %bb.4
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bb.4: ; preds = %sw.bb7.i.i.i3.i.i, %bb.3
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%phi.4 = phi <4 x i32> [ %phi.3, %bb.3 ], [ %insert.0, %sw.bb7.i.i.i3.i.i ]
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%extract = extractelement <4 x i32> %phi.4, i64 0
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store i32 %extract, ptr addrspace(5) null, align 4
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ret void
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}
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