e900f0584e
The aarch64 platform has special registers like X0_X1_X2_X3_X4_X5_X6_X7. Using the downwards propagation this register will become a super register for all X0..X7 and its super registers which is not right. This patch replaces the downwards propagation with caching all the aliases using MCRegAliasIterator. Vladislav Khmelevsky, Advanced Software Technology Lab, Huawei Reviewed By: maksfb Differential Revision: https://reviews.llvm.org/D117394
536 lines
17 KiB
C++
536 lines
17 KiB
C++
//===- bolt/Core/MCPlusBuilder.cpp - Interface for MCPlus -----------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the MCPlusBuilder class.
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//
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//===----------------------------------------------------------------------===//
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#include "bolt/Core/MCPlusBuilder.h"
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#include "bolt/Core/MCPlus.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrAnalysis.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/Support/Debug.h"
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#include <cstdint>
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#include <queue>
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#define DEBUG_TYPE "mcplus"
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using namespace llvm;
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using namespace bolt;
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using namespace MCPlus;
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bool MCPlusBuilder::equals(const MCInst &A, const MCInst &B,
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CompFuncTy Comp) const {
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if (A.getOpcode() != B.getOpcode())
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return false;
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unsigned NumOperands = MCPlus::getNumPrimeOperands(A);
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if (NumOperands != MCPlus::getNumPrimeOperands(B))
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return false;
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for (unsigned Index = 0; Index < NumOperands; ++Index)
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if (!equals(A.getOperand(Index), B.getOperand(Index), Comp))
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return false;
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return true;
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}
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bool MCPlusBuilder::equals(const MCOperand &A, const MCOperand &B,
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CompFuncTy Comp) const {
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if (A.isReg()) {
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if (!B.isReg())
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return false;
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return A.getReg() == B.getReg();
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} else if (A.isImm()) {
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if (!B.isImm())
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return false;
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return A.getImm() == B.getImm();
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} else if (A.isSFPImm()) {
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if (!B.isSFPImm())
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return false;
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return A.getSFPImm() == B.getSFPImm();
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} else if (A.isDFPImm()) {
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if (!B.isDFPImm())
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return false;
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return A.getDFPImm() == B.getDFPImm();
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} else if (A.isExpr()) {
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if (!B.isExpr())
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return false;
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return equals(*A.getExpr(), *B.getExpr(), Comp);
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} else {
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llvm_unreachable("unexpected operand kind");
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return false;
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}
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}
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bool MCPlusBuilder::equals(const MCExpr &A, const MCExpr &B,
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CompFuncTy Comp) const {
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if (A.getKind() != B.getKind())
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return false;
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switch (A.getKind()) {
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case MCExpr::Constant: {
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const auto &ConstA = cast<MCConstantExpr>(A);
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const auto &ConstB = cast<MCConstantExpr>(B);
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return ConstA.getValue() == ConstB.getValue();
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}
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case MCExpr::SymbolRef: {
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const MCSymbolRefExpr &SymbolA = cast<MCSymbolRefExpr>(A);
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const MCSymbolRefExpr &SymbolB = cast<MCSymbolRefExpr>(B);
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return SymbolA.getKind() == SymbolB.getKind() &&
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Comp(&SymbolA.getSymbol(), &SymbolB.getSymbol());
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}
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case MCExpr::Unary: {
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const auto &UnaryA = cast<MCUnaryExpr>(A);
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const auto &UnaryB = cast<MCUnaryExpr>(B);
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return UnaryA.getOpcode() == UnaryB.getOpcode() &&
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equals(*UnaryA.getSubExpr(), *UnaryB.getSubExpr(), Comp);
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}
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case MCExpr::Binary: {
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const auto &BinaryA = cast<MCBinaryExpr>(A);
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const auto &BinaryB = cast<MCBinaryExpr>(B);
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return BinaryA.getOpcode() == BinaryB.getOpcode() &&
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equals(*BinaryA.getLHS(), *BinaryB.getLHS(), Comp) &&
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equals(*BinaryA.getRHS(), *BinaryB.getRHS(), Comp);
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}
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case MCExpr::Target: {
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const auto &TargetExprA = cast<MCTargetExpr>(A);
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const auto &TargetExprB = cast<MCTargetExpr>(B);
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return equals(TargetExprA, TargetExprB, Comp);
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}
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}
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llvm_unreachable("Invalid expression kind!");
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}
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bool MCPlusBuilder::equals(const MCTargetExpr &A, const MCTargetExpr &B,
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CompFuncTy Comp) const {
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llvm_unreachable("target-specific expressions are unsupported");
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}
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void MCPlusBuilder::setTailCall(MCInst &Inst) {
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assert(!hasAnnotation(Inst, MCAnnotation::kTailCall));
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setAnnotationOpValue(Inst, MCAnnotation::kTailCall, true);
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}
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bool MCPlusBuilder::isTailCall(const MCInst &Inst) const {
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if (hasAnnotation(Inst, MCAnnotation::kTailCall))
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return true;
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if (getConditionalTailCall(Inst))
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return true;
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return false;
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}
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Optional<MCLandingPad> MCPlusBuilder::getEHInfo(const MCInst &Inst) const {
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if (!isCall(Inst))
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return NoneType();
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Optional<int64_t> LPSym =
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getAnnotationOpValue(Inst, MCAnnotation::kEHLandingPad);
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if (!LPSym)
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return NoneType();
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Optional<int64_t> Action =
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getAnnotationOpValue(Inst, MCAnnotation::kEHAction);
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if (!Action)
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return NoneType();
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return std::make_pair(reinterpret_cast<const MCSymbol *>(*LPSym),
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static_cast<uint64_t>(*Action));
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}
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void MCPlusBuilder::addEHInfo(MCInst &Inst, const MCLandingPad &LP) {
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if (isCall(Inst)) {
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assert(!getEHInfo(Inst));
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setAnnotationOpValue(Inst, MCAnnotation::kEHLandingPad,
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reinterpret_cast<int64_t>(LP.first));
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setAnnotationOpValue(Inst, MCAnnotation::kEHAction,
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static_cast<int64_t>(LP.second));
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}
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}
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int64_t MCPlusBuilder::getGnuArgsSize(const MCInst &Inst) const {
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Optional<int64_t> Value =
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getAnnotationOpValue(Inst, MCAnnotation::kGnuArgsSize);
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if (!Value)
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return -1LL;
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return *Value;
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}
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void MCPlusBuilder::addGnuArgsSize(MCInst &Inst, int64_t GnuArgsSize,
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AllocatorIdTy AllocId) {
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assert(GnuArgsSize >= 0 && "cannot set GNU_args_size to negative value");
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assert(getGnuArgsSize(Inst) == -1LL && "GNU_args_size already set");
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assert(isInvoke(Inst) && "GNU_args_size can only be set for invoke");
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setAnnotationOpValue(Inst, MCAnnotation::kGnuArgsSize, GnuArgsSize, AllocId);
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}
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uint64_t MCPlusBuilder::getJumpTable(const MCInst &Inst) const {
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Optional<int64_t> Value =
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getAnnotationOpValue(Inst, MCAnnotation::kJumpTable);
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if (!Value)
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return 0;
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return *Value;
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}
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uint16_t MCPlusBuilder::getJumpTableIndexReg(const MCInst &Inst) const {
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return getAnnotationAs<uint16_t>(Inst, "JTIndexReg");
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}
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bool MCPlusBuilder::setJumpTable(MCInst &Inst, uint64_t Value,
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uint16_t IndexReg, AllocatorIdTy AllocId) {
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if (!isIndirectBranch(Inst))
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return false;
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setAnnotationOpValue(Inst, MCAnnotation::kJumpTable, Value, AllocId);
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getOrCreateAnnotationAs<uint16_t>(Inst, "JTIndexReg", AllocId) = IndexReg;
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return true;
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}
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bool MCPlusBuilder::unsetJumpTable(MCInst &Inst) {
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if (!getJumpTable(Inst))
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return false;
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removeAnnotation(Inst, MCAnnotation::kJumpTable);
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removeAnnotation(Inst, "JTIndexReg");
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return true;
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}
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Optional<uint64_t>
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MCPlusBuilder::getConditionalTailCall(const MCInst &Inst) const {
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Optional<int64_t> Value =
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getAnnotationOpValue(Inst, MCAnnotation::kConditionalTailCall);
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if (!Value)
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return NoneType();
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return static_cast<uint64_t>(*Value);
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}
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bool MCPlusBuilder::setConditionalTailCall(MCInst &Inst, uint64_t Dest) {
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if (!isConditionalBranch(Inst))
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return false;
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setAnnotationOpValue(Inst, MCAnnotation::kConditionalTailCall, Dest);
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return true;
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}
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bool MCPlusBuilder::unsetConditionalTailCall(MCInst &Inst) {
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if (!getConditionalTailCall(Inst))
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return false;
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removeAnnotation(Inst, MCAnnotation::kConditionalTailCall);
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return true;
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}
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Optional<uint32_t> MCPlusBuilder::getOffset(const MCInst &Inst) const {
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Optional<int64_t> Value = getAnnotationOpValue(Inst, MCAnnotation::kOffset);
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if (!Value)
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return NoneType();
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return static_cast<uint32_t>(*Value);
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}
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uint32_t MCPlusBuilder::getOffsetWithDefault(const MCInst &Inst,
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uint32_t Default) const {
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if (Optional<uint32_t> Offset = getOffset(Inst))
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return *Offset;
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return Default;
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}
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bool MCPlusBuilder::setOffset(MCInst &Inst, uint32_t Offset,
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AllocatorIdTy AllocatorId) {
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setAnnotationOpValue(Inst, MCAnnotation::kOffset, Offset, AllocatorId);
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return true;
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}
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bool MCPlusBuilder::clearOffset(MCInst &Inst) {
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if (!hasAnnotation(Inst, MCAnnotation::kOffset))
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return false;
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removeAnnotation(Inst, MCAnnotation::kOffset);
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return true;
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}
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bool MCPlusBuilder::hasAnnotation(const MCInst &Inst, unsigned Index) const {
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const MCInst *AnnotationInst = getAnnotationInst(Inst);
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if (!AnnotationInst)
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return false;
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return (bool)getAnnotationOpValue(Inst, Index);
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}
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bool MCPlusBuilder::removeAnnotation(MCInst &Inst, unsigned Index) {
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MCInst *AnnotationInst = getAnnotationInst(Inst);
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if (!AnnotationInst)
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return false;
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for (int I = AnnotationInst->getNumOperands() - 1; I >= 0; --I) {
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int64_t ImmValue = AnnotationInst->getOperand(I).getImm();
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if (extractAnnotationIndex(ImmValue) == Index) {
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AnnotationInst->erase(AnnotationInst->begin() + I);
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return true;
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}
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}
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return false;
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}
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void MCPlusBuilder::stripAnnotations(MCInst &Inst, bool KeepTC) {
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MCInst *AnnotationInst = getAnnotationInst(Inst);
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if (!AnnotationInst)
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return;
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// Preserve TailCall annotation.
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auto IsTC = hasAnnotation(Inst, MCAnnotation::kTailCall);
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Inst.erase(std::prev(Inst.end()));
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if (KeepTC && IsTC)
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setTailCall(Inst);
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}
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void MCPlusBuilder::printAnnotations(const MCInst &Inst,
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raw_ostream &OS) const {
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const MCInst *AnnotationInst = getAnnotationInst(Inst);
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if (!AnnotationInst)
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return;
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for (unsigned I = 0; I < AnnotationInst->getNumOperands(); ++I) {
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const int64_t Imm = AnnotationInst->getOperand(I).getImm();
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const unsigned Index = extractAnnotationIndex(Imm);
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const int64_t Value = extractAnnotationValue(Imm);
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const auto *Annotation = reinterpret_cast<const MCAnnotation *>(Value);
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if (Index >= MCAnnotation::kGeneric) {
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OS << " # " << AnnotationNames[Index - MCAnnotation::kGeneric] << ": ";
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Annotation->print(OS);
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}
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}
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}
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bool MCPlusBuilder::evaluateBranch(const MCInst &Inst, uint64_t Addr,
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uint64_t Size, uint64_t &Target) const {
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return Analysis->evaluateBranch(Inst, Addr, Size, Target);
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}
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void MCPlusBuilder::getClobberedRegs(const MCInst &Inst,
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BitVector &Regs) const {
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if (isPrefix(Inst) || isCFI(Inst))
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return;
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const MCInstrDesc &InstInfo = Info->get(Inst.getOpcode());
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const MCPhysReg *ImplicitDefs = InstInfo.getImplicitDefs();
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for (unsigned I = 0, E = InstInfo.getNumImplicitDefs(); I != E; ++I)
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Regs |= getAliases(ImplicitDefs[I], /*OnlySmaller=*/false);
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for (unsigned I = 0, E = InstInfo.getNumDefs(); I != E; ++I) {
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const MCOperand &Operand = Inst.getOperand(I);
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assert(Operand.isReg());
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Regs |= getAliases(Operand.getReg(), /*OnlySmaller=*/false);
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}
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}
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void MCPlusBuilder::getTouchedRegs(const MCInst &Inst, BitVector &Regs) const {
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if (isPrefix(Inst) || isCFI(Inst))
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return;
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const MCInstrDesc &InstInfo = Info->get(Inst.getOpcode());
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const MCPhysReg *ImplicitDefs = InstInfo.getImplicitDefs();
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for (unsigned I = 0, E = InstInfo.getNumImplicitDefs(); I != E; ++I)
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Regs |= getAliases(ImplicitDefs[I], /*OnlySmaller=*/false);
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const MCPhysReg *ImplicitUses = InstInfo.getImplicitUses();
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for (unsigned I = 0, E = InstInfo.getNumImplicitUses(); I != E; ++I)
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Regs |= getAliases(ImplicitUses[I], /*OnlySmaller=*/false);
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for (unsigned I = 0, E = Inst.getNumOperands(); I != E; ++I) {
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if (!Inst.getOperand(I).isReg())
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continue;
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Regs |= getAliases(Inst.getOperand(I).getReg(), /*OnlySmaller=*/false);
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}
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}
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void MCPlusBuilder::getWrittenRegs(const MCInst &Inst, BitVector &Regs) const {
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if (isPrefix(Inst) || isCFI(Inst))
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return;
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const MCInstrDesc &InstInfo = Info->get(Inst.getOpcode());
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const MCPhysReg *ImplicitDefs = InstInfo.getImplicitDefs();
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for (unsigned I = 0, E = InstInfo.getNumImplicitDefs(); I != E; ++I)
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Regs |= getAliases(ImplicitDefs[I], /*OnlySmaller=*/true);
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for (unsigned I = 0, E = InstInfo.getNumDefs(); I != E; ++I) {
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const MCOperand &Operand = Inst.getOperand(I);
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assert(Operand.isReg());
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Regs |= getAliases(Operand.getReg(), /*OnlySmaller=*/true);
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}
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}
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void MCPlusBuilder::getUsedRegs(const MCInst &Inst, BitVector &Regs) const {
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if (isPrefix(Inst) || isCFI(Inst))
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return;
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const MCInstrDesc &InstInfo = Info->get(Inst.getOpcode());
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const MCPhysReg *ImplicitUses = InstInfo.getImplicitUses();
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for (unsigned I = 0, E = InstInfo.getNumImplicitUses(); I != E; ++I)
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Regs |= getAliases(ImplicitUses[I], /*OnlySmaller=*/true);
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for (unsigned I = 0, E = Inst.getNumOperands(); I != E; ++I) {
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if (!Inst.getOperand(I).isReg())
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continue;
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Regs |= getAliases(Inst.getOperand(I).getReg(), /*OnlySmaller=*/true);
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}
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}
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void MCPlusBuilder::getSrcRegs(const MCInst &Inst, BitVector &Regs) const {
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if (isPrefix(Inst) || isCFI(Inst))
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return;
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if (isCall(Inst)) {
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BitVector CallRegs = BitVector(Regs.size(), false);
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getCalleeSavedRegs(CallRegs);
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CallRegs.flip();
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Regs |= CallRegs;
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return;
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}
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if (isReturn(Inst)) {
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getDefaultLiveOut(Regs);
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return;
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}
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if (isRep(Inst))
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getRepRegs(Regs);
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const MCInstrDesc &InstInfo = Info->get(Inst.getOpcode());
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const MCPhysReg *ImplicitUses = InstInfo.getImplicitUses();
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for (unsigned I = 0, E = InstInfo.getNumImplicitUses(); I != E; ++I)
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Regs |= getAliases(ImplicitUses[I], /*OnlySmaller=*/true);
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for (unsigned I = InstInfo.getNumDefs(), E = InstInfo.getNumOperands();
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I != E; ++I) {
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if (!Inst.getOperand(I).isReg())
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continue;
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Regs |= getAliases(Inst.getOperand(I).getReg(), /*OnlySmaller=*/true);
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}
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}
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bool MCPlusBuilder::hasDefOfPhysReg(const MCInst &MI, unsigned Reg) const {
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const MCInstrDesc &InstInfo = Info->get(MI.getOpcode());
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return InstInfo.hasDefOfPhysReg(MI, Reg, *RegInfo);
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}
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bool MCPlusBuilder::hasUseOfPhysReg(const MCInst &MI, unsigned Reg) const {
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const MCInstrDesc &InstInfo = Info->get(MI.getOpcode());
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for (int I = InstInfo.NumDefs; I < InstInfo.NumOperands; ++I)
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if (MI.getOperand(I).isReg() &&
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RegInfo->isSubRegisterEq(Reg, MI.getOperand(I).getReg()))
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return true;
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if (const uint16_t *ImpUses = InstInfo.ImplicitUses) {
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for (; *ImpUses; ++ImpUses)
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if (*ImpUses == Reg || RegInfo->isSubRegister(Reg, *ImpUses))
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return true;
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}
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return false;
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}
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const BitVector &MCPlusBuilder::getAliases(MCPhysReg Reg,
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bool OnlySmaller) const {
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// AliasMap caches a mapping of registers to the set of registers that
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// alias (are sub or superregs of itself, including itself).
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static std::vector<BitVector> AliasMap;
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static std::vector<BitVector> SmallerAliasMap;
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if (AliasMap.size() > 0) {
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if (OnlySmaller)
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return SmallerAliasMap[Reg];
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return AliasMap[Reg];
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}
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// Build alias map
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for (MCPhysReg I = 0, E = RegInfo->getNumRegs(); I != E; ++I) {
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BitVector BV(RegInfo->getNumRegs(), false);
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BV.set(I);
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AliasMap.emplace_back(BV);
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SmallerAliasMap.emplace_back(BV);
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}
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// Cache all aliases for each register
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for (MCPhysReg I = 1, E = RegInfo->getNumRegs(); I != E; ++I) {
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for (MCRegAliasIterator AI(I, RegInfo, true); AI.isValid(); ++AI)
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AliasMap[I].set(*AI);
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}
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// Propagate smaller alias info upwards. Skip reg 0 (mapped to NoRegister)
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std::queue<MCPhysReg> Worklist;
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for (MCPhysReg I = 1, E = RegInfo->getNumRegs(); I < E; ++I)
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Worklist.push(I);
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while (!Worklist.empty()) {
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MCPhysReg I = Worklist.front();
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Worklist.pop();
|
|
for (MCSubRegIterator SI(I, RegInfo); SI.isValid(); ++SI)
|
|
SmallerAliasMap[I] |= SmallerAliasMap[*SI];
|
|
for (MCSuperRegIterator SI(I, RegInfo); SI.isValid(); ++SI)
|
|
Worklist.push(*SI);
|
|
}
|
|
|
|
LLVM_DEBUG({
|
|
dbgs() << "Dumping reg alias table:\n";
|
|
for (MCPhysReg I = 0, E = RegInfo->getNumRegs(); I != E; ++I) {
|
|
dbgs() << "Reg " << I << ": ";
|
|
const BitVector &BV = AliasMap[I];
|
|
int Idx = BV.find_first();
|
|
while (Idx != -1) {
|
|
dbgs() << Idx << " ";
|
|
Idx = BV.find_next(Idx);
|
|
}
|
|
dbgs() << "\n";
|
|
}
|
|
});
|
|
|
|
if (OnlySmaller)
|
|
return SmallerAliasMap[Reg];
|
|
return AliasMap[Reg];
|
|
}
|
|
|
|
uint8_t MCPlusBuilder::getRegSize(MCPhysReg Reg) const {
|
|
// SizeMap caches a mapping of registers to their sizes
|
|
static std::vector<uint8_t> SizeMap;
|
|
|
|
if (SizeMap.size() > 0) {
|
|
return SizeMap[Reg];
|
|
}
|
|
SizeMap = std::vector<uint8_t>(RegInfo->getNumRegs());
|
|
// Build size map
|
|
for (auto I = RegInfo->regclass_begin(), E = RegInfo->regclass_end(); I != E;
|
|
++I) {
|
|
for (MCPhysReg Reg : *I)
|
|
SizeMap[Reg] = I->getSizeInBits() / 8;
|
|
}
|
|
|
|
return SizeMap[Reg];
|
|
}
|
|
|
|
bool MCPlusBuilder::setOperandToSymbolRef(MCInst &Inst, int OpNum,
|
|
const MCSymbol *Symbol,
|
|
int64_t Addend, MCContext *Ctx,
|
|
uint64_t RelType) const {
|
|
MCOperand Operand;
|
|
if (!Addend) {
|
|
Operand = MCOperand::createExpr(getTargetExprFor(
|
|
Inst, MCSymbolRefExpr::create(Symbol, *Ctx), *Ctx, RelType));
|
|
} else {
|
|
Operand = MCOperand::createExpr(getTargetExprFor(
|
|
Inst,
|
|
MCBinaryExpr::createAdd(MCSymbolRefExpr::create(Symbol, *Ctx),
|
|
MCConstantExpr::create(Addend, *Ctx), *Ctx),
|
|
*Ctx, RelType));
|
|
}
|
|
Inst.getOperand(OpNum) = Operand;
|
|
return true;
|
|
}
|