362ea5f2c3
This patch moves the construction of the default backend from llvm-mca.cpp and into mca::Context. The Context class is responsible for holding ownership of the simulated hardware components. These components are subclasses of HardwareUnit. Right now the HardwareUnit is pretty bare-bones, but eventually we might want to add some common functionality across all hardware components, such as isReady() or something similar. I have a feeling this patch will probably need some updates, but it's a start. One thing I am not particularly fond of is the rather large interface for createDefaultPipeline. That convenience routine takes a rather large set of inputs from the llvm-mca driver, where many of those inputs are generated via command line options. One item I think we might want to change is the separating of ownership of hardware components (owned by the context) and the pipeline (which owns Stages). In short, a Pipeline owns Stages, a Context (currently) owns hardware. The Pipeline's Stages make use of the components, and thus there is a lifetime dependency generated. The components must outlive the pipeline. We could solve this by having the Context also own the Pipeline, and not return a unique_ptr<Pipeline>. Now that I think about it, I like that idea more. Differential Revision: https://reviews.llvm.org/D48691 llvm-svn: 336456
69 lines
2.3 KiB
C++
69 lines
2.3 KiB
C++
//===---------------------------- Context.h ---------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// This file defines a class for holding ownership of various simulated
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/// hardware units. A Context also provides a utility routine for constructing
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/// a default out-of-order pipeline with fetch, dispatch, execute, and retire
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/// stages).
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TOOLS_LLVM_MCA_CONTEXT_H
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#define LLVM_TOOLS_LLVM_MCA_CONTEXT_H
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#include "HardwareUnit.h"
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#include "InstrBuilder.h"
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#include "Pipeline.h"
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#include "SourceMgr.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSchedule.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include <memory>
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namespace mca {
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/// This is a convenience struct to hold the parameters necessary for creating
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/// the pre-built "default" out-of-order pipeline.
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struct PipelineOptions {
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PipelineOptions(unsigned DW, unsigned RFS, unsigned LQS, unsigned SQS,
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bool NoAlias)
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: DispatchWidth(DW), RegisterFileSize(RFS), LoadQueueSize(LQS),
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StoreQueueSize(SQS), AssumeNoAlias(NoAlias) {}
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unsigned DispatchWidth;
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unsigned RegisterFileSize;
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unsigned LoadQueueSize;
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unsigned StoreQueueSize;
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bool AssumeNoAlias;
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};
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class Context {
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llvm::SmallVector<std::unique_ptr<HardwareUnit>, 4> Hardware;
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const llvm::MCRegisterInfo &MRI;
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const llvm::MCSubtargetInfo &STI;
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public:
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Context(const llvm::MCRegisterInfo &R, const llvm::MCSubtargetInfo &S)
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: MRI(R), STI(S) {}
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Context(const Context &C) = delete;
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Context &operator=(const Context &C) = delete;
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void addHardwareUnit(std::unique_ptr<HardwareUnit> H) {
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Hardware.push_back(std::move(H));
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}
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/// Construct a basic pipeline for simulating an out-of-order pipeline.
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/// This pipeline consists of Fetch, Dispatch, Execute, and Retire stages.
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std::unique_ptr<Pipeline> createDefaultPipeline(const PipelineOptions &Opts,
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InstrBuilder &IB,
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SourceMgr &SrcMgr);
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};
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} // namespace mca
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#endif // LLVM_TOOLS_LLVM_MCA_CONTEXT_H
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