e9f22fd429
This patch generates TableGen descriptions for the specified register banks which contain a list of register sizes corresponding to the available HwModes. The appropriate size is used during codegen according to the current HwMode. As this HwMode was not available on generation, it is set upon construction of the RegisterBankInfo class. Targets simply need to provide the HwMode argument to the <target>GenRegisterBankInfo constructor. The RISC-V RegisterBankInfo constructor has been updated accordingly (plus an unused argument removed). Differential Revision: https://reviews.llvm.org/D76007
80 lines
2.6 KiB
C++
80 lines
2.6 KiB
C++
//===-- RISCVSubtarget.cpp - RISCV Subtarget Information ------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the RISCV specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVSubtarget.h"
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#include "RISCV.h"
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#include "RISCVCallLowering.h"
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#include "RISCVFrameLowering.h"
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#include "RISCVLegalizerInfo.h"
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#include "RISCVRegisterBankInfo.h"
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#include "RISCVTargetMachine.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define DEBUG_TYPE "riscv-subtarget"
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#define GET_SUBTARGETINFO_TARGET_DESC
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#define GET_SUBTARGETINFO_CTOR
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#include "RISCVGenSubtargetInfo.inc"
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void RISCVSubtarget::anchor() {}
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RISCVSubtarget &RISCVSubtarget::initializeSubtargetDependencies(
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const Triple &TT, StringRef CPU, StringRef FS, StringRef ABIName) {
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// Determine default and user-specified characteristics
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bool Is64Bit = TT.isArch64Bit();
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std::string CPUName = std::string(CPU);
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if (CPUName.empty())
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CPUName = Is64Bit ? "generic-rv64" : "generic-rv32";
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ParseSubtargetFeatures(CPUName, FS);
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if (Is64Bit) {
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XLenVT = MVT::i64;
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XLen = 64;
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}
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TargetABI = RISCVABI::computeTargetABI(TT, getFeatureBits(), ABIName);
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RISCVFeatures::validate(TT, getFeatureBits());
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return *this;
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}
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RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
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StringRef ABIName, const TargetMachine &TM)
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: RISCVGenSubtargetInfo(TT, CPU, FS),
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UserReservedRegister(RISCV::NUM_TARGET_REGS),
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FrameLowering(initializeSubtargetDependencies(TT, CPU, FS, ABIName)),
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InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {
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CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering()));
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Legalizer.reset(new RISCVLegalizerInfo(*this));
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auto *RBI = new RISCVRegisterBankInfo(getHwMode());
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RegBankInfo.reset(RBI);
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InstSelector.reset(createRISCVInstructionSelector(
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*static_cast<const RISCVTargetMachine *>(&TM), *this, *RBI));
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}
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const CallLowering *RISCVSubtarget::getCallLowering() const {
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return CallLoweringInfo.get();
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}
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InstructionSelector *RISCVSubtarget::getInstructionSelector() const {
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return InstSelector.get();
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}
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const LegalizerInfo *RISCVSubtarget::getLegalizerInfo() const {
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return Legalizer.get();
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}
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const RegisterBankInfo *RISCVSubtarget::getRegBankInfo() const {
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return RegBankInfo.get();
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}
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