161a158e5c
Support all instructions with VOP1 encoding with 32 or 64-bit operands for VI subtarget: VGPR_32 and VReg_64 operand register classes VS_32 and VS_64 operand register classes with inline and literal constants Tests for VOP1 instructions. Patch by: skolton Reviewers: arsenm, tstellarAMD Review: http://reviews.llvm.org/D17194 llvm-svn: 261878
81 lines
3.1 KiB
C++
81 lines
3.1 KiB
C++
//===-- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA ---*- C++ -*--===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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///
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/// This file contains declaration for AMDGPU ISA disassembler
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
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#define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
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#include "llvm/MC/MCDisassembler/MCDisassembler.h"
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namespace llvm {
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class MCContext;
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class MCInst;
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class MCSubtargetInfo;
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class AMDGPUDisassembler : public MCDisassembler {
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private:
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/// true if 32-bit literal constant is placed after instruction
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mutable bool HasLiteral;
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mutable ArrayRef<uint8_t> Bytes;
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public:
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AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
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MCDisassembler(STI, Ctx), HasLiteral(false) {}
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~AMDGPUDisassembler() {}
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DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &WS, raw_ostream &CS) const override;
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/// Decode inline float value in SRC field
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DecodeStatus DecodeImmedFloat(unsigned Imm, uint32_t &F) const;
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/// Decode inline double value in SRC field
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DecodeStatus DecodeImmedDouble(unsigned Imm, uint64_t &D) const;
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/// Decode inline integer value in SRC field
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DecodeStatus DecodeImmedInteger(unsigned Imm, int64_t &I) const;
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/// Decode VGPR register
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DecodeStatus DecodeVgprRegister(unsigned Val, unsigned &RegID,
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unsigned Size = 32) const;
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/// Decode SGPR register
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DecodeStatus DecodeSgprRegister(unsigned Val, unsigned &RegID,
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unsigned Size = 32) const;
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/// Decode 32-bit register in SRC field
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DecodeStatus DecodeSrc32Register(unsigned Val, unsigned &RegID) const;
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/// Decode 64-bit register in SRC field
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DecodeStatus DecodeSrc64Register(unsigned Val, unsigned &RegID) const;
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/// Decode literal constant after instruction
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DecodeStatus DecodeLiteralConstant(MCInst &Inst, uint64_t &Literal) const;
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DecodeStatus DecodeVGPR_32RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr) const;
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DecodeStatus DecodeVSRegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr, bool Is32) const;
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DecodeStatus DecodeVS_32RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr) const;
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DecodeStatus DecodeVS_64RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr) const;
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DecodeStatus DecodeVReg_64RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr) const;
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};
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} // namespace llvm
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#endif // LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
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