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llvm-project/llvm/lib/Target/RISCV
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Craig Topper 247eb13fab [RISCV][GISel] Legalize G_BITREVERSE.
2023-11-09 16:27:21 -08:00
..
AsmParser
[RISCV][NFC] Pass MCSubtargetInfo instead of FeatureBitset in RISCVMatInt (#71770)
2023-11-09 15:15:23 +08:00
Disassembler
[RISCV] Support Xsfvfnrclipxfqf extensions (#68297)
2023-11-03 10:52:37 +08:00
GISel
[RISCV][GISel] Legalize G_BITREVERSE.
2023-11-09 16:27:21 -08:00
MCA
[RISCV] Keep same SEW/LMUL ratio if possible in forward transfer (#69788)
2023-10-27 12:16:28 +01:00
MCTargetDesc
[RISCV] Support R_RISCV_SET_ULEB128/R_RISCV_SUB_ULEB128 for .uleb128 directives
2023-11-09 09:27:32 -08:00
TargetInfo
…
CMakeLists.txt
[RISCV] Implement cross basic block VXRM write insertion. (#70382)
2023-11-02 14:09:27 -07:00
RISCV.h
[RISCV] Implement cross basic block VXRM write insertion. (#70382)
2023-11-02 14:09:27 -07:00
RISCV.td
…
RISCVAsmPrinter.cpp
[RISCV] Add Stackmap/Statepoint/Patchpoint support without targets
2023-10-11 09:18:55 +05:30
RISCVCallingConv.td
[RISCV] Simplify the definitions of interrupt CSRs
2023-07-11 11:20:24 +08:00
RISCVCodeGenPrepare.cpp
[RISCV] Rewrite RISCVCodeGenPrepare using zext nneg [nfc-ish] (#70739)
2023-10-30 16:35:30 -07:00
RISCVCombine.td
[RISCV][GISel] Add a post legalizer combiner and enable a couple comb… (#67053)
2023-09-22 10:13:56 -07:00
RISCVDeadRegisterDefinitions.cpp
[RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose return values are unused
2023-09-20 01:02:19 +08:00
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] Prevent tryToFoldBNEOnCmpXchgResult from deleting AND if it has others users.
2023-08-28 10:11:12 -07:00
RISCVExpandPseudoInsts.cpp
[RISCV] Add more instructions for the short forward branch optimization. (#66789)
2023-09-19 10:21:39 -07:00
RISCVFeatures.td
[RISCV] Introduce and use BF16 in Xsfvfwmaccqqq intrinsics (#71140)
2023-11-06 11:22:14 +08:00
RISCVFoldMasks.cpp
[RISCV] Begin moving post-isel vector peepholes to a MF pass (#70342)
2023-10-30 15:17:00 +00:00
RISCVFrameLowering.cpp
[RISCV] Fix wrong offset use caused by missing the size of Zcmp push. (#66613)
2023-09-25 12:05:05 +08:00
RISCVFrameLowering.h
[llvm] Fix duplicate word typos. NFC
2023-09-01 18:25:16 -07:00
RISCVGatherScatterLowering.cpp
[RISCV] Match constant indices of non-index type when forming strided ops (#65777)
2023-09-18 09:41:34 -07:00
RISCVGISel.td
[RISCV] Don't promote i32 and/or/xor with -riscv-experimental-rv64-legal-i32.
2023-11-01 11:36:46 -07:00
RISCVInsertReadWriteCSR.cpp
[RISCV] Implement cross basic block VXRM write insertion. (#70382)
2023-11-02 14:09:27 -07:00
RISCVInsertVSETVLI.cpp
[RISCVInsertVSETVLI] Allow PRE with non-immediate AVLs (#71728)
2023-11-09 08:03:13 -08:00
RISCVInsertWriteVXRM.cpp
[RISCV] Implement cross basic block VXRM write insertion. (#70382)
2023-11-02 14:09:27 -07:00
RISCVInstrFormats.td
[RISCV][NFC] Remove rdty arg of PseudoLoad and the default rdty value of PseudoFloatLoad (#67014)
2023-09-23 01:21:28 +08:00
RISCVInstrFormatsC.td
[RISCV] Remove unused Opcode field from RVInst16. NFC
2023-07-20 08:18:06 -07:00
RISCVInstrFormatsV.td
[RISCV] Remove Opcode field from RVInst. Assign Inst{6-0} directly. NFC
2023-07-20 08:18:06 -07:00
RISCVInstrInfo.cpp
[RISCV][NFC] Pass MCSubtargetInfo instead of FeatureBitset in RISCVMatInt (#71770)
2023-11-09 15:15:23 +08:00
RISCVInstrInfo.h
[RISCV] CSE by swapping conditional branches (#71111)
2023-11-03 09:03:52 -07:00
RISCVInstrInfo.td
[RISCV] Add (i32 (and GPR:, TrailingOnesMask:)) pattern for RV64 with legal i32.
2023-11-02 15:03:05 -07:00
RISCVInstrInfoA.td
[RISCV] Add experimental support for making i32 a legal type on RV64 in SelectionDAG. (#70357)
2023-11-01 09:36:41 -07:00
RISCVInstrInfoC.td
[RISCV] Add CompressPat for c.beqz/bnez with X0 in the first operand. (#69042)
2023-10-14 08:12:46 -07:00
RISCVInstrInfoD.td
[RISCV] Add experimental support for making i32 a legal type on RV64 in SelectionDAG. (#70357)
2023-11-01 09:36:41 -07:00
RISCVInstrInfoF.td
[RISCV] Add experimental support for making i32 a legal type on RV64 in SelectionDAG. (#70357)
2023-11-01 09:36:41 -07:00
RISCVInstrInfoM.td
[RISCV] Add experimental support for making i32 a legal type on RV64 in SelectionDAG. (#70357)
2023-11-01 09:36:41 -07:00
RISCVInstrInfoV.td
[RISCV][NFC] Add base classes of Operand and uimm/simm (#68472)
2023-10-08 14:13:08 +08:00
RISCVInstrInfoVPseudos.td
[RISCV] Use masked pseudo peephole for reduction pseudos (#71508)
2023-11-08 12:46:06 +08:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Support select/merge like ops for fp16 vectors when only have Zvfhmin
2023-09-27 14:53:14 +08:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Use masked pseudo peephole for reduction pseudos (#71508)
2023-11-08 12:46:06 +08:00
RISCVInstrInfoXCV.td
[RISCV][NFC] Rename CVROR, NFC
2023-08-20 16:36:03 +10:00
RISCVInstrInfoXSf.td
[RISCV] Support Xsfvfnrclipxfqf extensions (#68297)
2023-11-03 10:52:37 +08:00
RISCVInstrInfoXTHead.td
[RISCV] Add experimental support for making i32 a legal type on RV64 in SelectionDAG. (#70357)
2023-11-01 09:36:41 -07:00
RISCVInstrInfoXVentana.td
[RISCV] Rename Ventana DecoderNamespace to XVentana for matching other extension. NFC.
2023-08-19 12:44:59 +08:00
RISCVInstrInfoZb.td
[RISCV] Disable Zbs special case in performTRUNCATECombine with -riscv-experimental-rv64-legal-i32.
2023-11-09 10:19:28 -08:00
RISCVInstrInfoZc.td
[RISCV][NFC] Correct RISCVInstrInfoZc.td header comment - Zc* extensions no longer experimental
2023-10-10 16:41:27 +01:00
RISCVInstrInfoZfa.td
[RISCV] Apply IsSignExtendingOpW = 1 on fcvtmod.w.d (#69633)
2023-10-19 14:55:33 -07:00
RISCVInstrInfoZfbfmin.td
[RISCV] Add experimental support for making i32 a legal type on RV64 in SelectionDAG. (#70357)
2023-11-01 09:36:41 -07:00
RISCVInstrInfoZfh.td
[RISCV] Add experimental support for making i32 a legal type on RV64 in SelectionDAG. (#70357)
2023-11-01 09:36:41 -07:00
RISCVInstrInfoZicbo.td
[RISCV] Match prefetch address with offset (#66072)
2023-10-20 14:22:48 +08:00
RISCVInstrInfoZicond.td
[RISCV] Handle seteq/setne conditions for CZERO_NEZ/CZERO_EQZ during isel.
2023-07-26 10:06:08 -07:00
RISCVInstrInfoZk.td
[RISCV][NFC] Add base classes of Operand and uimm/simm (#68472)
2023-10-08 14:13:08 +08:00
RISCVInstrInfoZvfbf.td
[RISCV] Model all 3 arithmetic sources of vector FMA at MC layer.
2023-08-04 09:08:16 -07:00
RISCVInstrInfoZvk.td
[RISCV] Fix wrong implication for zvknhb. (#66860)
2023-11-03 09:32:21 +08:00
RISCVISelDAGToDAG.cpp
[RISCV][NFC] Pass MCSubtargetInfo instead of FeatureBitset in RISCVMatInt (#71770)
2023-11-09 15:15:23 +08:00
RISCVISelDAGToDAG.h
[RISCV] Disable performCombineVMergeAndVOps for PseduoVIOTA_M. (#71483)
2023-11-07 16:21:35 +08:00
RISCVISelLowering.cpp
[RISCV] Disable Zbs special case in performTRUNCATECombine with -riscv-experimental-rv64-legal-i32.
2023-11-09 10:19:28 -08:00
RISCVISelLowering.h
[VP][RISCV] Add llvm.experimental.vp.reverse. (#70405)
2023-11-05 22:39:27 -08:00
RISCVMachineFunctionInfo.cpp
…
RISCVMachineFunctionInfo.h
[RISCV] Fix wrong offset use caused by missing the size of Zcmp push. (#66613)
2023-09-25 12:05:05 +08:00
RISCVMacroFusion.cpp
[RISCV] Remove FrameIndex case in lui+addi MacroFusion (#68701)
2023-10-19 13:32:44 +08:00
RISCVMacroFusion.h
…
RISCVMakeCompressible.cpp
[RegScavenger] Simplify state tracking for backwards scavenging (#71202)
2023-11-08 09:49:07 +00:00
RISCVMergeBaseOffset.cpp
[RISCV] Teach RISCVMergeBaseOffset to handle BlockAddress
2023-09-18 11:47:14 +08:00
RISCVMoveMerger.cpp
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-10-21 10:52:24 -07:00
RISCVOptWInstrs.cpp
[RISCV] Teach RISCVOptWInstrs that 'bset x0, 30-0' satisfies isSignExtendingOpW.
2023-11-01 12:29:37 -07:00
RISCVPostRAExpandPseudoInsts.cpp
[RISCV][NFC] Pass MCSubtargetInfo instead of FeatureBitset in RISCVMatInt (#71770)
2023-11-09 15:15:23 +08:00
RISCVProcessors.td
[RISCV] Add processor definition for XiangShan-NanHu (#70294)
2023-11-08 00:41:06 +08:00
RISCVPushPopOptimizer.cpp
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-10-21 10:52:24 -07:00
RISCVRedundantCopyElimination.cpp
…
RISCVRegisterInfo.cpp
[RISCV] Mark V0 regclasses as larger superclasses of non-V0 classes (#70109)
2023-10-24 22:13:17 +01:00
RISCVRegisterInfo.h
…
RISCVRegisterInfo.td
[RISCV][NFC] Use !range bang operator (#66494)
2023-10-20 12:06:01 +08:00
RISCVRVVInitUndef.cpp
[RISCV] Add sink-and-fold support for RISC-V. (#67602)
2023-10-07 10:38:35 -07:00
RISCVSchedRocket.td
[RISCV] Separate addend from FMA operands to support cascade FMA. NFC. (#70241)
2023-10-26 13:00:36 +08:00
RISCVSchedSiFive7.td
[RISCV] SiFive7 VLDS Sched should not depend on VL when stride is x0. (#70266)
2023-10-30 15:47:45 -04:00
RISCVSchedSyntacoreSCR1.td
[RISCV] Separate addend from FMA operands to support cascade FMA. NFC. (#70241)
2023-10-26 13:00:36 +08:00
RISCVSchedule.td
[RISCV] Separate addend from FMA operands to support cascade FMA. NFC. (#70241)
2023-10-26 13:00:36 +08:00
RISCVScheduleV.td
[RISCV] SiFive7 VLDS Sched should not depend on VL when stride is x0. (#70266)
2023-10-30 15:47:45 -04:00
RISCVScheduleZb.td
[RISCV] Split BEXT and BEXTI Write classes. NFC.
2023-07-17 15:52:40 -07:00
RISCVSubtarget.cpp
[RISCV] Add searchable table for tune information (#66193)
2023-09-26 12:26:35 +08:00
RISCVSubtarget.h
[RISCV] Add TuneVentanaVeyron subtarget feature. (#70414)
2023-10-31 00:37:30 -04:00
RISCVSystemOperands.td
[RISCV] Add support for custom CSRs for Sifive S76.
2023-07-14 09:51:15 -07:00
RISCVTargetMachine.cpp
[RISCV] Implement cross basic block VXRM write insertion. (#70382)
2023-11-02 14:09:27 -07:00
RISCVTargetMachine.h
[NFC][CodeGen] Change CodeGenOpt::Level/CodeGenFileType into enum classes (#66295)
2023-09-14 14:10:14 -07:00
RISCVTargetObjectFile.cpp
[RISCV] RISCVELFTargetObjectFile: use 2-byte alignment for .text if RVC
2023-05-11 13:44:37 -07:00
RISCVTargetObjectFile.h
[RISCV] RISCVELFTargetObjectFile: use 2-byte alignment for .text if RVC
2023-05-11 13:44:37 -07:00
RISCVTargetTransformInfo.cpp
[RISCV][NFC] Pass MCSubtargetInfo instead of FeatureBitset in RISCVMatInt (#71770)
2023-11-09 15:15:23 +08:00
RISCVTargetTransformInfo.h
[RISCV][CostModel] Add getCFInstrCost RISC-V implementation (#65599)
2023-09-25 12:26:01 +03:00