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llvm-project/llvm/test/CodeGen/Mips/cconv
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Simon Atanasyan 623282f0dd [mips] Explicitly select mips32r2 CPU for test cases require 64-bit FPU. NFC
Support for 64-bit coprocessors on a 32-bit architecture
was added in `MIPS32 R2`.

llvm-svn: 365507
2019-07-09 15:48:05 +00:00
..
arguments-float.ll
…
arguments-fp128.ll
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arguments-hard-float-varargs.ll
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arguments-hard-float.ll
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arguments-hard-fp128.ll
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arguments-small-structures-bigger-than-32bits.ll
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arguments-struct.ll
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arguments-varargs-small-structs-byte.ll
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arguments-varargs-small-structs-combinations.ll
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arguments-varargs-small-structs-multiple-args.ll
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arguments-varargs.ll
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arguments.ll
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byval.ll
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callee-saved-float.ll
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callee-saved-fpxx1.ll
[mips] Explicitly select mips32r2 CPU for test cases require 64-bit FPU. NFC
2019-07-09 15:48:05 +00:00
callee-saved-fpxx.ll
…
callee-saved.ll
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fmaxl_call.ll
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memory-layout.ll
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pr33883.ll
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reserved-space.ll
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return-float.ll
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return-hard-float.ll
[mips] Explicitly select mips32r2 CPU for test cases require 64-bit FPU. NFC
2019-07-09 15:48:05 +00:00
return-hard-fp128.ll
…
return-hard-struct-f128.ll
…
return-struct.ll
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return.ll
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roundl-call.ll
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stack-alignment.ll
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vector.ll
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