b5efec4b27
With D134950, targets get notified when a virtual register is created and/or cloned. Targets can do the needful with the delegate callback. AMDGPU propagates the virtual register flags maintained in the target file itself. They are useful to identify a certain type of machine operands while inserting spill stores and reloads. Since RegAllocFast spills the physical register itself, there is no way its virtual register can be mapped back to retrieve the flags. It can be solved by passing the virtual register as an additional argument. This argument has no use when the spill interfaces are called during the greedy allocator or even the PrologEpilogInserter and can pass a null register in such cases. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D138656
63 lines
2.4 KiB
C++
63 lines
2.4 KiB
C++
//===-- Thumb1InstrInfo.h - Thumb-1 Instruction Information -----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Thumb-1 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_THUMB1INSTRINFO_H
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#define LLVM_LIB_TARGET_ARM_THUMB1INSTRINFO_H
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#include "ARMBaseInstrInfo.h"
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#include "ThumbRegisterInfo.h"
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namespace llvm {
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class ARMSubtarget;
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class Thumb1InstrInfo : public ARMBaseInstrInfo {
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ThumbRegisterInfo RI;
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public:
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explicit Thumb1InstrInfo(const ARMSubtarget &STI);
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/// Return the noop instruction to use for a noop.
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MCInst getNop() const override;
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// Return the non-pre/post incrementing version of 'Opc'. Return 0
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// if there is not such an opcode.
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unsigned getUnindexedOpcode(unsigned Opc) const override;
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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const ThumbRegisterInfo &getRegisterInfo() const override { return RI; }
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
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bool KillSrc) const override;
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, Register SrcReg,
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bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI,
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Register VReg) const override;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, Register DestReg,
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int FrameIndex, const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI,
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Register VReg) const override;
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bool canCopyGluedNodeDuringSchedule(SDNode *N) const override;
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private:
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void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override;
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};
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}
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#endif
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