45137766ca
Following https://github.com/llvm/llvm-project/pull/68313 this patch extends the idea to M-profile PACBTI. The Machine Scheduler can reorder instructions within a scheduling region depending on the scheduling policy set. If a BTI-clearing instruction happens to partake in one such region, it might be moved around, therefore ending up where it shouldn't. The solution is to mark all BTI-clearing instructions as scheduling region boundaries. This essentially means that they must not be part of any scheduling region, and as consequence never get moved: - PAC - PACBTI - BTI - SG Note that PAC isn't BTI-clearing, but it's replaced by PACBTI late in the compilation pipeline. As far as I know, currently it isn't possible to organically obtain code that's susceptible to the bug: - Instructions that write to SP are region boundaries. PAC seems to always be followed by the pushing of r12 to the stack, so essentially PAC is always by itself in a scheduling region. - CALL_BTI is expanded into a machine instruction bundle. Bundles are unpacked only after the last machine scheduler run. Thus setjmp and BTI can be separated only if someone deliberately run the scheduler once more. - The BTI insertion pass is run late in the pipeline, only after the last machine scheduling has run. So once again it can be reordered only if someone deliberately runs the scheduler again. Nevertheless, one can reasonably argue that we should prevent the bug in spite of the compiler not being able to produce the required conditions for it. If things change, the compiler will be robust against this issue. The tests written for this are contrived: bogus MIR instructions have been added adjacent to the BTI-clearing instructions in order to have them inside non-trivial scheduling regions.
103 lines
4.3 KiB
C++
103 lines
4.3 KiB
C++
//===-- Thumb2InstrInfo.h - Thumb-2 Instruction Information -----*- C++ -*-===//
|
|
//
|
|
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
|
// See https://llvm.org/LICENSE.txt for license information.
|
|
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file contains the Thumb-2 implementation of the TargetInstrInfo class.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef LLVM_LIB_TARGET_ARM_THUMB2INSTRINFO_H
|
|
#define LLVM_LIB_TARGET_ARM_THUMB2INSTRINFO_H
|
|
|
|
#include "ARMBaseInstrInfo.h"
|
|
#include "ThumbRegisterInfo.h"
|
|
|
|
namespace llvm {
|
|
class ARMSubtarget;
|
|
|
|
class Thumb2InstrInfo : public ARMBaseInstrInfo {
|
|
ThumbRegisterInfo RI;
|
|
public:
|
|
explicit Thumb2InstrInfo(const ARMSubtarget &STI);
|
|
|
|
/// Return the noop instruction to use for a noop.
|
|
MCInst getNop() const override;
|
|
|
|
// Return the non-pre/post incrementing version of 'Opc'. Return 0
|
|
// if there is not such an opcode.
|
|
unsigned getUnindexedOpcode(unsigned Opc) const override;
|
|
|
|
void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
|
|
MachineBasicBlock *NewDest) const override;
|
|
|
|
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MBBI) const override;
|
|
|
|
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
|
|
bool KillSrc) const override;
|
|
|
|
void storeRegToStackSlot(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MBBI, Register SrcReg,
|
|
bool isKill, int FrameIndex,
|
|
const TargetRegisterClass *RC,
|
|
const TargetRegisterInfo *TRI,
|
|
Register VReg) const override;
|
|
|
|
void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MBBI, Register DestReg,
|
|
int FrameIndex, const TargetRegisterClass *RC,
|
|
const TargetRegisterInfo *TRI,
|
|
Register VReg) const override;
|
|
|
|
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
|
|
/// such, whenever a client has an instance of instruction info, it should
|
|
/// always be able to get register info as well (through this method).
|
|
///
|
|
const ThumbRegisterInfo &getRegisterInfo() const override { return RI; }
|
|
|
|
MachineInstr *optimizeSelect(MachineInstr &MI,
|
|
SmallPtrSetImpl<MachineInstr *> &SeenMIs,
|
|
bool) const override;
|
|
|
|
MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
|
|
unsigned OpIdx1,
|
|
unsigned OpIdx2) const override;
|
|
|
|
bool isSchedulingBoundary(const MachineInstr &MI,
|
|
const MachineBasicBlock *MBB,
|
|
const MachineFunction &MF) const override;
|
|
|
|
private:
|
|
void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override;
|
|
};
|
|
|
|
/// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical
|
|
/// to llvm::getInstrPredicate except it returns AL for conditional branch
|
|
/// instructions which are "predicated", but are not in IT blocks.
|
|
ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, Register &PredReg);
|
|
|
|
// getVPTInstrPredicate: VPT analogue of that, plus a helper function
|
|
// corresponding to MachineInstr::findFirstPredOperandIdx.
|
|
int findFirstVPTPredOperandIdx(const MachineInstr &MI);
|
|
ARMVCC::VPTCodes getVPTInstrPredicate(const MachineInstr &MI,
|
|
Register &PredReg);
|
|
inline ARMVCC::VPTCodes getVPTInstrPredicate(const MachineInstr &MI) {
|
|
Register PredReg;
|
|
return getVPTInstrPredicate(MI, PredReg);
|
|
}
|
|
|
|
// Recomputes the Block Mask of Instr, a VPT or VPST instruction.
|
|
// This rebuilds the block mask of the instruction depending on the predicates
|
|
// of the instructions following it. This should only be used after the
|
|
// MVEVPTBlockInsertion pass has run, and should be used whenever a predicated
|
|
// instruction is added to/removed from the block.
|
|
void recomputeVPTBlockMask(MachineInstr &Instr);
|
|
} // namespace llvm
|
|
|
|
#endif
|