01f79899ba
In LoongArch psABI v2.30, the R_LARCH_ALIGN requires symbol index to support the third parameter of alignment directive. Create symbol for each section is redundant because they have section symbol which can also be used as symbol index. So use section symbol directly for R_LARCH_ALIGN.
518 lines
19 KiB
C++
518 lines
19 KiB
C++
//===-- LoongArchAsmBackend.cpp - LoongArch Assembler Backend -*- C++ -*---===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the LoongArchAsmBackend class.
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//
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//===----------------------------------------------------------------------===//
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#include "LoongArchAsmBackend.h"
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#include "LoongArchFixupKinds.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCAsmLayout.h"
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#include "llvm/MC/MCAssembler.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCSection.h"
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#include "llvm/MC/MCValue.h"
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#include "llvm/Support/EndianStream.h"
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#include "llvm/Support/LEB128.h"
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#include "llvm/Support/MathExtras.h"
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#define DEBUG_TYPE "loongarch-asmbackend"
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using namespace llvm;
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std::optional<MCFixupKind>
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LoongArchAsmBackend::getFixupKind(StringRef Name) const {
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if (STI.getTargetTriple().isOSBinFormatELF()) {
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auto Type = llvm::StringSwitch<unsigned>(Name)
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#define ELF_RELOC(X, Y) .Case(#X, Y)
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#include "llvm/BinaryFormat/ELFRelocs/LoongArch.def"
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#undef ELF_RELOC
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.Case("BFD_RELOC_NONE", ELF::R_LARCH_NONE)
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.Case("BFD_RELOC_32", ELF::R_LARCH_32)
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.Case("BFD_RELOC_64", ELF::R_LARCH_64)
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.Default(-1u);
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if (Type != -1u)
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return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
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}
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return std::nullopt;
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}
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const MCFixupKindInfo &
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LoongArchAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
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const static MCFixupKindInfo Infos[] = {
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// This table *must* be in the order that the fixup_* kinds are defined in
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// LoongArchFixupKinds.h.
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//
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// {name, offset, bits, flags}
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{"fixup_loongarch_b16", 10, 16, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_loongarch_b21", 0, 26, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_loongarch_b26", 0, 26, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_loongarch_abs_hi20", 5, 20, 0},
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{"fixup_loongarch_abs_lo12", 10, 12, 0},
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{"fixup_loongarch_abs64_lo20", 5, 20, 0},
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{"fixup_loongarch_abs64_hi12", 10, 12, 0},
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{"fixup_loongarch_tls_le_hi20", 5, 20, 0},
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{"fixup_loongarch_tls_le_lo12", 10, 12, 0},
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{"fixup_loongarch_tls_le64_lo20", 5, 20, 0},
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{"fixup_loongarch_tls_le64_hi12", 10, 12, 0},
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// TODO: Add more fixup kinds.
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};
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static_assert((std::size(Infos)) == LoongArch::NumTargetFixupKinds,
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"Not all fixup kinds added to Infos array");
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// Fixup kinds from .reloc directive are like R_LARCH_NONE. They
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// do not require any extra processing.
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if (Kind >= FirstLiteralRelocationKind)
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return MCAsmBackend::getFixupKindInfo(FK_NONE);
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if (Kind < FirstTargetFixupKind)
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return MCAsmBackend::getFixupKindInfo(Kind);
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assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
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"Invalid kind!");
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return Infos[Kind - FirstTargetFixupKind];
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}
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static void reportOutOfRangeError(MCContext &Ctx, SMLoc Loc, unsigned N) {
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Ctx.reportError(Loc, "fixup value out of range [" + Twine(llvm::minIntN(N)) +
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", " + Twine(llvm::maxIntN(N)) + "]");
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}
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static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
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MCContext &Ctx) {
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switch (Fixup.getTargetKind()) {
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default:
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llvm_unreachable("Unknown fixup kind");
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case FK_Data_1:
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case FK_Data_2:
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case FK_Data_4:
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case FK_Data_8:
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case FK_Data_leb128:
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return Value;
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case LoongArch::fixup_loongarch_b16: {
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if (!isInt<18>(Value))
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reportOutOfRangeError(Ctx, Fixup.getLoc(), 18);
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if (Value % 4)
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Ctx.reportError(Fixup.getLoc(), "fixup value must be 4-byte aligned");
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return (Value >> 2) & 0xffff;
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}
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case LoongArch::fixup_loongarch_b21: {
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if (!isInt<23>(Value))
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reportOutOfRangeError(Ctx, Fixup.getLoc(), 23);
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if (Value % 4)
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Ctx.reportError(Fixup.getLoc(), "fixup value must be 4-byte aligned");
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return ((Value & 0x3fffc) << 8) | ((Value >> 18) & 0x1f);
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}
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case LoongArch::fixup_loongarch_b26: {
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if (!isInt<28>(Value))
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reportOutOfRangeError(Ctx, Fixup.getLoc(), 28);
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if (Value % 4)
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Ctx.reportError(Fixup.getLoc(), "fixup value must be 4-byte aligned");
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return ((Value & 0x3fffc) << 8) | ((Value >> 18) & 0x3ff);
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}
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case LoongArch::fixup_loongarch_abs_hi20:
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case LoongArch::fixup_loongarch_tls_le_hi20:
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return (Value >> 12) & 0xfffff;
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case LoongArch::fixup_loongarch_abs_lo12:
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case LoongArch::fixup_loongarch_tls_le_lo12:
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return Value & 0xfff;
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case LoongArch::fixup_loongarch_abs64_lo20:
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case LoongArch::fixup_loongarch_tls_le64_lo20:
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return (Value >> 32) & 0xfffff;
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case LoongArch::fixup_loongarch_abs64_hi12:
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case LoongArch::fixup_loongarch_tls_le64_hi12:
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return (Value >> 52) & 0xfff;
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}
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}
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static void fixupLeb128(MCContext &Ctx, const MCFixup &Fixup,
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MutableArrayRef<char> Data, uint64_t Value) {
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unsigned I;
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for (I = 0; I != Data.size() && Value; ++I, Value >>= 7)
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Data[I] |= uint8_t(Value & 0x7f);
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if (Value)
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Ctx.reportError(Fixup.getLoc(), "Invalid uleb128 value!");
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}
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void LoongArchAsmBackend::applyFixup(const MCAssembler &Asm,
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const MCFixup &Fixup,
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const MCValue &Target,
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MutableArrayRef<char> Data, uint64_t Value,
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bool IsResolved,
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const MCSubtargetInfo *STI) const {
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if (!Value)
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return; // Doesn't change encoding.
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MCFixupKind Kind = Fixup.getKind();
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if (Kind >= FirstLiteralRelocationKind)
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return;
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MCFixupKindInfo Info = getFixupKindInfo(Kind);
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MCContext &Ctx = Asm.getContext();
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// Fixup leb128 separately.
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if (Fixup.getTargetKind() == FK_Data_leb128)
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return fixupLeb128(Ctx, Fixup, Data, Value);
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// Apply any target-specific value adjustments.
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Value = adjustFixupValue(Fixup, Value, Ctx);
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// Shift the value into position.
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Value <<= Info.TargetOffset;
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unsigned Offset = Fixup.getOffset();
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unsigned NumBytes = alignTo(Info.TargetSize + Info.TargetOffset, 8) / 8;
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assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
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// For each byte of the fragment that the fixup touches, mask in the
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// bits from the fixup value.
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for (unsigned I = 0; I != NumBytes; ++I) {
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Data[Offset + I] |= uint8_t((Value >> (I * 8)) & 0xff);
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}
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}
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// Linker relaxation may change code size. We have to insert Nops
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// for .align directive when linker relaxation enabled. So then Linker
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// could satisfy alignment by removing Nops.
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// The function returns the total Nops Size we need to insert.
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bool LoongArchAsmBackend::shouldInsertExtraNopBytesForCodeAlign(
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const MCAlignFragment &AF, unsigned &Size) {
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// Calculate Nops Size only when linker relaxation enabled.
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if (!AF.getSubtargetInfo()->hasFeature(LoongArch::FeatureRelax))
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return false;
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// Ignore alignment if MaxBytesToEmit is less than the minimum Nop size.
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const unsigned MinNopLen = 4;
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if (AF.getMaxBytesToEmit() < MinNopLen)
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return false;
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Size = AF.getAlignment().value() - MinNopLen;
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return AF.getAlignment() > MinNopLen;
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}
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// We need to insert R_LARCH_ALIGN relocation type to indicate the
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// position of Nops and the total bytes of the Nops have been inserted
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// when linker relaxation enabled.
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// The function inserts fixup_loongarch_align fixup which eventually will
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// transfer to R_LARCH_ALIGN relocation type.
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// The improved R_LARCH_ALIGN requires symbol index. The lowest 8 bits of
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// addend represent alignment and the other bits of addend represent the
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// maximum number of bytes to emit. The maximum number of bytes is zero
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// means ignore the emit limit.
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bool LoongArchAsmBackend::shouldInsertFixupForCodeAlign(
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MCAssembler &Asm, const MCAsmLayout &Layout, MCAlignFragment &AF) {
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// Insert the fixup only when linker relaxation enabled.
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if (!AF.getSubtargetInfo()->hasFeature(LoongArch::FeatureRelax))
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return false;
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// Calculate total Nops we need to insert. If there are none to insert
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// then simply return.
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unsigned Count;
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if (!shouldInsertExtraNopBytesForCodeAlign(AF, Count))
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return false;
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MCSection *Sec = AF.getParent();
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MCContext &Ctx = Asm.getContext();
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const MCExpr *Dummy = MCConstantExpr::create(0, Ctx);
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// Create fixup_loongarch_align fixup.
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MCFixup Fixup =
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MCFixup::create(0, Dummy, MCFixupKind(LoongArch::fixup_loongarch_align));
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const MCSymbolRefExpr *MCSym = getSecToAlignSym()[Sec];
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if (MCSym == nullptr) {
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// Use section symbol directly.
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MCSym = MCSymbolRefExpr::create(Sec->getBeginSymbol(), Ctx);
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getSecToAlignSym()[Sec] = MCSym;
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}
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uint64_t FixedValue = 0;
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unsigned Lo = Log2_64(Count) + 1;
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unsigned Hi = AF.getMaxBytesToEmit() >= Count ? 0 : AF.getMaxBytesToEmit();
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MCValue Value = MCValue::get(MCSym, nullptr, Hi << 8 | Lo);
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Asm.getWriter().recordRelocation(Asm, Layout, &AF, Fixup, Value, FixedValue);
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return true;
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}
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bool LoongArchAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
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const MCFixup &Fixup,
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const MCValue &Target,
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const MCSubtargetInfo *STI) {
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if (Fixup.getKind() >= FirstLiteralRelocationKind)
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return true;
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switch (Fixup.getTargetKind()) {
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default:
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return STI->hasFeature(LoongArch::FeatureRelax);
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case FK_Data_1:
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case FK_Data_2:
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case FK_Data_4:
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case FK_Data_8:
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case FK_Data_leb128:
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return !Target.isAbsolute();
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}
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}
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static inline std::pair<MCFixupKind, MCFixupKind>
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getRelocPairForSize(unsigned Size) {
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switch (Size) {
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default:
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llvm_unreachable("unsupported fixup size");
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case 6:
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return std::make_pair(
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MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_ADD6),
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MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_SUB6));
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case 8:
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return std::make_pair(
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MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_ADD8),
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MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_SUB8));
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case 16:
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return std::make_pair(
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MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_ADD16),
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MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_SUB16));
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case 32:
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return std::make_pair(
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MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_ADD32),
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MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_SUB32));
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case 64:
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return std::make_pair(
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MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_ADD64),
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MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_SUB64));
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case 128:
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return std::make_pair(
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MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_ADD_ULEB128),
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MCFixupKind(FirstLiteralRelocationKind + ELF::R_LARCH_SUB_ULEB128));
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}
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}
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std::pair<bool, bool> LoongArchAsmBackend::relaxLEB128(MCLEBFragment &LF,
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MCAsmLayout &Layout,
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int64_t &Value) const {
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const MCExpr &Expr = LF.getValue();
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if (LF.isSigned() || !Expr.evaluateKnownAbsolute(Value, Layout))
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return std::make_pair(false, false);
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LF.getFixups().push_back(
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MCFixup::create(0, &Expr, FK_Data_leb128, Expr.getLoc()));
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return std::make_pair(true, true);
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}
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bool LoongArchAsmBackend::relaxDwarfLineAddr(MCDwarfLineAddrFragment &DF,
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MCAsmLayout &Layout,
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bool &WasRelaxed) const {
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MCContext &C = Layout.getAssembler().getContext();
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int64_t LineDelta = DF.getLineDelta();
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const MCExpr &AddrDelta = DF.getAddrDelta();
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SmallVectorImpl<char> &Data = DF.getContents();
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SmallVectorImpl<MCFixup> &Fixups = DF.getFixups();
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size_t OldSize = Data.size();
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int64_t Value;
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if (AddrDelta.evaluateAsAbsolute(Value, Layout))
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return false;
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bool IsAbsolute = AddrDelta.evaluateKnownAbsolute(Value, Layout);
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assert(IsAbsolute && "CFA with invalid expression");
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(void)IsAbsolute;
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Data.clear();
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Fixups.clear();
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raw_svector_ostream OS(Data);
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// INT64_MAX is a signal that this is actually a DW_LNE_end_sequence.
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if (LineDelta != INT64_MAX) {
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OS << uint8_t(dwarf::DW_LNS_advance_line);
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encodeSLEB128(LineDelta, OS);
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}
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unsigned Offset;
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std::pair<MCFixupKind, MCFixupKind> FK;
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// According to the DWARF specification, the `DW_LNS_fixed_advance_pc` opcode
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// takes a single unsigned half (unencoded) operand. The maximum encodable
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// value is therefore 65535. Set a conservative upper bound for relaxation.
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if (Value > 60000) {
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unsigned PtrSize = C.getAsmInfo()->getCodePointerSize();
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OS << uint8_t(dwarf::DW_LNS_extended_op);
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encodeULEB128(PtrSize + 1, OS);
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OS << uint8_t(dwarf::DW_LNE_set_address);
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Offset = OS.tell();
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assert((PtrSize == 4 || PtrSize == 8) && "Unexpected pointer size");
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FK = getRelocPairForSize(PtrSize == 4 ? 32 : 64);
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OS.write_zeros(PtrSize);
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} else {
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OS << uint8_t(dwarf::DW_LNS_fixed_advance_pc);
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Offset = OS.tell();
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FK = getRelocPairForSize(16);
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support::endian::write<uint16_t>(OS, 0, llvm::endianness::little);
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}
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const MCBinaryExpr &MBE = cast<MCBinaryExpr>(AddrDelta);
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Fixups.push_back(MCFixup::create(Offset, MBE.getLHS(), std::get<0>(FK)));
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Fixups.push_back(MCFixup::create(Offset, MBE.getRHS(), std::get<1>(FK)));
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if (LineDelta == INT64_MAX) {
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OS << uint8_t(dwarf::DW_LNS_extended_op);
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OS << uint8_t(1);
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OS << uint8_t(dwarf::DW_LNE_end_sequence);
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} else {
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OS << uint8_t(dwarf::DW_LNS_copy);
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}
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WasRelaxed = OldSize != Data.size();
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return true;
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}
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bool LoongArchAsmBackend::relaxDwarfCFA(MCDwarfCallFrameFragment &DF,
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MCAsmLayout &Layout,
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bool &WasRelaxed) const {
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const MCExpr &AddrDelta = DF.getAddrDelta();
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SmallVectorImpl<char> &Data = DF.getContents();
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SmallVectorImpl<MCFixup> &Fixups = DF.getFixups();
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size_t OldSize = Data.size();
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int64_t Value;
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if (AddrDelta.evaluateAsAbsolute(Value, Layout))
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return false;
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bool IsAbsolute = AddrDelta.evaluateKnownAbsolute(Value, Layout);
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assert(IsAbsolute && "CFA with invalid expression");
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(void)IsAbsolute;
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Data.clear();
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Fixups.clear();
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raw_svector_ostream OS(Data);
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assert(
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Layout.getAssembler().getContext().getAsmInfo()->getMinInstAlignment() ==
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1 &&
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"expected 1-byte alignment");
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if (Value == 0) {
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WasRelaxed = OldSize != Data.size();
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return true;
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}
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auto AddFixups = [&Fixups,
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&AddrDelta](unsigned Offset,
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std::pair<MCFixupKind, MCFixupKind> FK) {
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const MCBinaryExpr &MBE = cast<MCBinaryExpr>(AddrDelta);
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Fixups.push_back(MCFixup::create(Offset, MBE.getLHS(), std::get<0>(FK)));
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Fixups.push_back(MCFixup::create(Offset, MBE.getRHS(), std::get<1>(FK)));
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};
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if (isUIntN(6, Value)) {
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OS << uint8_t(dwarf::DW_CFA_advance_loc);
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AddFixups(0, getRelocPairForSize(6));
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} else if (isUInt<8>(Value)) {
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OS << uint8_t(dwarf::DW_CFA_advance_loc1);
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support::endian::write<uint8_t>(OS, 0, llvm::endianness::little);
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AddFixups(1, getRelocPairForSize(8));
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} else if (isUInt<16>(Value)) {
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OS << uint8_t(dwarf::DW_CFA_advance_loc2);
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support::endian::write<uint16_t>(OS, 0, llvm::endianness::little);
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AddFixups(1, getRelocPairForSize(16));
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} else if (isUInt<32>(Value)) {
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OS << uint8_t(dwarf::DW_CFA_advance_loc4);
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support::endian::write<uint32_t>(OS, 0, llvm::endianness::little);
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AddFixups(1, getRelocPairForSize(32));
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} else {
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llvm_unreachable("unsupported CFA encoding");
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}
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WasRelaxed = OldSize != Data.size();
|
|
return true;
|
|
}
|
|
|
|
bool LoongArchAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
|
|
const MCSubtargetInfo *STI) const {
|
|
// We mostly follow binutils' convention here: align to 4-byte boundary with a
|
|
// 0-fill padding.
|
|
OS.write_zeros(Count % 4);
|
|
|
|
// The remainder is now padded with 4-byte nops.
|
|
// nop: andi r0, r0, 0
|
|
for (; Count >= 4; Count -= 4)
|
|
OS.write("\0\0\x40\x03", 4);
|
|
|
|
return true;
|
|
}
|
|
|
|
bool LoongArchAsmBackend::handleAddSubRelocations(const MCAsmLayout &Layout,
|
|
const MCFragment &F,
|
|
const MCFixup &Fixup,
|
|
const MCValue &Target,
|
|
uint64_t &FixedValue) const {
|
|
std::pair<MCFixupKind, MCFixupKind> FK;
|
|
uint64_t FixedValueA, FixedValueB;
|
|
const MCSymbol &SA = Target.getSymA()->getSymbol();
|
|
const MCSymbol &SB = Target.getSymB()->getSymbol();
|
|
|
|
bool force = !SA.isInSection() || !SB.isInSection();
|
|
if (!force) {
|
|
const MCSection &SecA = SA.getSection();
|
|
const MCSection &SecB = SB.getSection();
|
|
|
|
// We need record relocation if SecA != SecB. Usually SecB is same as the
|
|
// section of Fixup, which will be record the relocation as PCRel. If SecB
|
|
// is not same as the section of Fixup, it will report error. Just return
|
|
// false and then this work can be finished by handleFixup.
|
|
if (&SecA != &SecB)
|
|
return false;
|
|
|
|
// In SecA == SecB case. If the linker relaxation is enabled, we need record
|
|
// the ADD, SUB relocations. Otherwise the FixedValue has already been calc-
|
|
// ulated out in evaluateFixup, return true and avoid record relocations.
|
|
if (!STI.hasFeature(LoongArch::FeatureRelax))
|
|
return true;
|
|
}
|
|
|
|
switch (Fixup.getKind()) {
|
|
case llvm::FK_Data_1:
|
|
FK = getRelocPairForSize(8);
|
|
break;
|
|
case llvm::FK_Data_2:
|
|
FK = getRelocPairForSize(16);
|
|
break;
|
|
case llvm::FK_Data_4:
|
|
FK = getRelocPairForSize(32);
|
|
break;
|
|
case llvm::FK_Data_8:
|
|
FK = getRelocPairForSize(64);
|
|
break;
|
|
case llvm::FK_Data_leb128:
|
|
FK = getRelocPairForSize(128);
|
|
break;
|
|
default:
|
|
llvm_unreachable("unsupported fixup size");
|
|
}
|
|
MCValue A = MCValue::get(Target.getSymA(), nullptr, Target.getConstant());
|
|
MCValue B = MCValue::get(Target.getSymB());
|
|
auto FA = MCFixup::create(Fixup.getOffset(), nullptr, std::get<0>(FK));
|
|
auto FB = MCFixup::create(Fixup.getOffset(), nullptr, std::get<1>(FK));
|
|
auto &Asm = Layout.getAssembler();
|
|
Asm.getWriter().recordRelocation(Asm, Layout, &F, FA, A, FixedValueA);
|
|
Asm.getWriter().recordRelocation(Asm, Layout, &F, FB, B, FixedValueB);
|
|
FixedValue = FixedValueA - FixedValueB;
|
|
return true;
|
|
}
|
|
|
|
std::unique_ptr<MCObjectTargetWriter>
|
|
LoongArchAsmBackend::createObjectTargetWriter() const {
|
|
return createLoongArchELFObjectWriter(
|
|
OSABI, Is64Bit, STI.hasFeature(LoongArch::FeatureRelax));
|
|
}
|
|
|
|
MCAsmBackend *llvm::createLoongArchAsmBackend(const Target &T,
|
|
const MCSubtargetInfo &STI,
|
|
const MCRegisterInfo &MRI,
|
|
const MCTargetOptions &Options) {
|
|
const Triple &TT = STI.getTargetTriple();
|
|
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
|
|
return new LoongArchAsmBackend(STI, OSABI, TT.isArch64Bit(), Options);
|
|
}
|