f768083516
This PR contains a series of fixes which are to improve type inference and instruction selection. Namely, it includes: * fix OpSelect to support operands of a pointer type, according to the SPIR-V specification (previously only integer/float/vectors of integer or float were supported) -- a new test case is added and existing test case is updated; * fix TableGen typo's in definition of register classes and introduce a new reg class that is a vector of pointers; * fix usage of a machine function context when there is a need to switch between different machine functions to infer/validate correct types; * add usage of TypedPointerType instead of PointerType so that later stages of type inference are able to distinguish pointer types by their element types, effectively supporting hierarchy of pointer/pointee types and avoiding more complicated recursive type matching on level of machine instructions in favor of direct pointer comparison using LLVM's `Type *` values; * extracting detailed information about operand types using known type rules for some llvm instructions (for instance, by deducing PHI's operand pointee types if PHI's results type was deducted on previous stages of type inference), and adding correspondent `Intrinsic::spv_assign_ptr_type` to keep type info along consequent passes, * ensure that OpConstantComposite reuses a constant when it's already created and available in the same machine function -- otherwise there is a crash while building a dependency graph, the corresponding test case is attached, * implement deduction of function's return type for opaque pointers, a new test case is attached, * make 'emit intrinsics' a module pass to resolve function return types over the module -- first types for all functions of the module must be calculated, and only after that it's feasible to deduct function return types on this earlier stage of translation.
578 lines
23 KiB
C++
578 lines
23 KiB
C++
//===-- SPIRVPreLegalizer.cpp - prepare IR for legalization -----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// The pass prepares IR for legalization: it assigns SPIR-V types to registers
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// and removes intrinsics which holded these types during IR translation.
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// Also it processes constants and registers them in GR to avoid duplication.
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//
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//===----------------------------------------------------------------------===//
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#include "SPIRV.h"
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#include "SPIRVSubtarget.h"
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#include "SPIRVUtils.h"
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#include "llvm/ADT/PostOrderIterator.h"
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#include "llvm/Analysis/OptimizationRemarkEmitter.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/DebugInfoMetadata.h"
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#include "llvm/IR/IntrinsicsSPIRV.h"
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#include "llvm/Target/TargetIntrinsicInfo.h"
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#define DEBUG_TYPE "spirv-prelegalizer"
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using namespace llvm;
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namespace {
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class SPIRVPreLegalizer : public MachineFunctionPass {
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public:
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static char ID;
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SPIRVPreLegalizer() : MachineFunctionPass(ID) {
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initializeSPIRVPreLegalizerPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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};
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} // namespace
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static void addConstantsToTrack(MachineFunction &MF, SPIRVGlobalRegistry *GR) {
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MachineRegisterInfo &MRI = MF.getRegInfo();
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DenseMap<MachineInstr *, Register> RegsAlreadyAddedToDT;
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SmallVector<MachineInstr *, 10> ToErase, ToEraseComposites;
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for (MachineBasicBlock &MBB : MF) {
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for (MachineInstr &MI : MBB) {
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if (!isSpvIntrinsic(MI, Intrinsic::spv_track_constant))
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continue;
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ToErase.push_back(&MI);
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auto *Const =
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cast<Constant>(cast<ConstantAsMetadata>(
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MI.getOperand(3).getMetadata()->getOperand(0))
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->getValue());
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if (auto *GV = dyn_cast<GlobalValue>(Const)) {
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Register Reg = GR->find(GV, &MF);
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if (!Reg.isValid())
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GR->add(GV, &MF, MI.getOperand(2).getReg());
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else
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RegsAlreadyAddedToDT[&MI] = Reg;
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} else {
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Register Reg = GR->find(Const, &MF);
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if (!Reg.isValid()) {
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if (auto *ConstVec = dyn_cast<ConstantDataVector>(Const)) {
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auto *BuildVec = MRI.getVRegDef(MI.getOperand(2).getReg());
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assert(BuildVec &&
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BuildVec->getOpcode() == TargetOpcode::G_BUILD_VECTOR);
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for (unsigned i = 0; i < ConstVec->getNumElements(); ++i) {
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// Ensure that OpConstantComposite reuses a constant when it's
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// already created and available in the same machine function.
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Constant *ElemConst = ConstVec->getElementAsConstant(i);
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Register ElemReg = GR->find(ElemConst, &MF);
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if (!ElemReg.isValid())
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GR->add(ElemConst, &MF, BuildVec->getOperand(1 + i).getReg());
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else
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BuildVec->getOperand(1 + i).setReg(ElemReg);
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}
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}
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GR->add(Const, &MF, MI.getOperand(2).getReg());
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} else {
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RegsAlreadyAddedToDT[&MI] = Reg;
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// This MI is unused and will be removed. If the MI uses
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// const_composite, it will be unused and should be removed too.
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assert(MI.getOperand(2).isReg() && "Reg operand is expected");
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MachineInstr *SrcMI = MRI.getVRegDef(MI.getOperand(2).getReg());
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if (SrcMI && isSpvIntrinsic(*SrcMI, Intrinsic::spv_const_composite))
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ToEraseComposites.push_back(SrcMI);
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}
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}
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}
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}
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for (MachineInstr *MI : ToErase) {
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Register Reg = MI->getOperand(2).getReg();
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if (RegsAlreadyAddedToDT.contains(MI))
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Reg = RegsAlreadyAddedToDT[MI];
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auto *RC = MRI.getRegClassOrNull(MI->getOperand(0).getReg());
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if (!MRI.getRegClassOrNull(Reg) && RC)
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MRI.setRegClass(Reg, RC);
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MRI.replaceRegWith(MI->getOperand(0).getReg(), Reg);
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MI->eraseFromParent();
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}
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for (MachineInstr *MI : ToEraseComposites)
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MI->eraseFromParent();
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}
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static void foldConstantsIntoIntrinsics(MachineFunction &MF) {
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SmallVector<MachineInstr *, 10> ToErase;
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MachineRegisterInfo &MRI = MF.getRegInfo();
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const unsigned AssignNameOperandShift = 2;
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for (MachineBasicBlock &MBB : MF) {
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for (MachineInstr &MI : MBB) {
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if (!isSpvIntrinsic(MI, Intrinsic::spv_assign_name))
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continue;
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unsigned NumOp = MI.getNumExplicitDefs() + AssignNameOperandShift;
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while (MI.getOperand(NumOp).isReg()) {
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MachineOperand &MOp = MI.getOperand(NumOp);
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MachineInstr *ConstMI = MRI.getVRegDef(MOp.getReg());
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assert(ConstMI->getOpcode() == TargetOpcode::G_CONSTANT);
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MI.removeOperand(NumOp);
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MI.addOperand(MachineOperand::CreateImm(
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ConstMI->getOperand(1).getCImm()->getZExtValue()));
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if (MRI.use_empty(ConstMI->getOperand(0).getReg()))
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ToErase.push_back(ConstMI);
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}
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}
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}
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for (MachineInstr *MI : ToErase)
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MI->eraseFromParent();
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}
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static void insertBitcasts(MachineFunction &MF, SPIRVGlobalRegistry *GR,
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MachineIRBuilder MIB) {
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// Get access to information about available extensions
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const SPIRVSubtarget *ST =
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static_cast<const SPIRVSubtarget *>(&MIB.getMF().getSubtarget());
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SmallVector<MachineInstr *, 10> ToErase;
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for (MachineBasicBlock &MBB : MF) {
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for (MachineInstr &MI : MBB) {
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if (!isSpvIntrinsic(MI, Intrinsic::spv_bitcast) &&
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!isSpvIntrinsic(MI, Intrinsic::spv_ptrcast))
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continue;
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assert(MI.getOperand(2).isReg());
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MIB.setInsertPt(*MI.getParent(), MI);
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ToErase.push_back(&MI);
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if (isSpvIntrinsic(MI, Intrinsic::spv_bitcast)) {
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MIB.buildBitcast(MI.getOperand(0).getReg(), MI.getOperand(2).getReg());
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continue;
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}
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Register Def = MI.getOperand(0).getReg();
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Register Source = MI.getOperand(2).getReg();
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SPIRVType *BaseTy = GR->getOrCreateSPIRVType(
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getMDOperandAsType(MI.getOperand(3).getMetadata(), 0), MIB);
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SPIRVType *AssignedPtrType = GR->getOrCreateSPIRVPointerType(
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BaseTy, MI, *MF.getSubtarget<SPIRVSubtarget>().getInstrInfo(),
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addressSpaceToStorageClass(MI.getOperand(4).getImm(), *ST));
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// If the bitcast would be redundant, replace all uses with the source
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// register.
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if (GR->getSPIRVTypeForVReg(Source) == AssignedPtrType) {
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MIB.getMRI()->replaceRegWith(Def, Source);
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} else {
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GR->assignSPIRVTypeToVReg(AssignedPtrType, Def, MF);
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MIB.buildBitcast(Def, Source);
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}
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}
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}
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for (MachineInstr *MI : ToErase)
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MI->eraseFromParent();
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}
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// Translating GV, IRTranslator sometimes generates following IR:
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// %1 = G_GLOBAL_VALUE
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// %2 = COPY %1
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// %3 = G_ADDRSPACE_CAST %2
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// New registers have no SPIRVType and no register class info.
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//
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// Set SPIRVType for GV, propagate it from GV to other instructions,
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// also set register classes.
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static SPIRVType *propagateSPIRVType(MachineInstr *MI, SPIRVGlobalRegistry *GR,
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MachineRegisterInfo &MRI,
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MachineIRBuilder &MIB) {
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SPIRVType *SpirvTy = nullptr;
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assert(MI && "Machine instr is expected");
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if (MI->getOperand(0).isReg()) {
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Register Reg = MI->getOperand(0).getReg();
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SpirvTy = GR->getSPIRVTypeForVReg(Reg);
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if (!SpirvTy) {
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switch (MI->getOpcode()) {
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case TargetOpcode::G_CONSTANT: {
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MIB.setInsertPt(*MI->getParent(), MI);
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Type *Ty = MI->getOperand(1).getCImm()->getType();
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SpirvTy = GR->getOrCreateSPIRVType(Ty, MIB);
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break;
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}
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case TargetOpcode::G_GLOBAL_VALUE: {
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MIB.setInsertPt(*MI->getParent(), MI);
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const GlobalValue *Global = MI->getOperand(1).getGlobal();
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Type *ElementTy = GR->getDeducedGlobalValueType(Global);
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auto *Ty = TypedPointerType::get(ElementTy,
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Global->getType()->getAddressSpace());
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SpirvTy = GR->getOrCreateSPIRVType(Ty, MIB);
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break;
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}
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case TargetOpcode::G_TRUNC:
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case TargetOpcode::G_ADDRSPACE_CAST:
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case TargetOpcode::G_PTR_ADD:
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case TargetOpcode::COPY: {
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MachineOperand &Op = MI->getOperand(1);
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MachineInstr *Def = Op.isReg() ? MRI.getVRegDef(Op.getReg()) : nullptr;
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if (Def)
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SpirvTy = propagateSPIRVType(Def, GR, MRI, MIB);
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break;
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}
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default:
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break;
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}
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if (SpirvTy)
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GR->assignSPIRVTypeToVReg(SpirvTy, Reg, MIB.getMF());
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if (!MRI.getRegClassOrNull(Reg))
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MRI.setRegClass(Reg, &SPIRV::IDRegClass);
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}
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}
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return SpirvTy;
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}
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static std::pair<Register, unsigned>
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createNewIdReg(Register ValReg, unsigned Opcode, MachineRegisterInfo &MRI,
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const SPIRVGlobalRegistry &GR) {
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LLT NewT = LLT::scalar(32);
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SPIRVType *SpvType = GR.getSPIRVTypeForVReg(ValReg);
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assert(SpvType && "VReg is expected to have SPIRV type");
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bool IsFloat = SpvType->getOpcode() == SPIRV::OpTypeFloat;
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bool IsVectorFloat =
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SpvType->getOpcode() == SPIRV::OpTypeVector &&
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GR.getSPIRVTypeForVReg(SpvType->getOperand(1).getReg())->getOpcode() ==
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SPIRV::OpTypeFloat;
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IsFloat |= IsVectorFloat;
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auto GetIdOp = IsFloat ? SPIRV::GET_fID : SPIRV::GET_ID;
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auto DstClass = IsFloat ? &SPIRV::fIDRegClass : &SPIRV::IDRegClass;
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if (MRI.getType(ValReg).isPointer()) {
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NewT = LLT::pointer(0, 32);
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GetIdOp = SPIRV::GET_pID;
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DstClass = &SPIRV::pIDRegClass;
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} else if (MRI.getType(ValReg).isVector()) {
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NewT = LLT::fixed_vector(2, NewT);
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GetIdOp = IsFloat ? SPIRV::GET_vfID : SPIRV::GET_vID;
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DstClass = IsFloat ? &SPIRV::vfIDRegClass : &SPIRV::vIDRegClass;
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}
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Register IdReg = MRI.createGenericVirtualRegister(NewT);
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MRI.setRegClass(IdReg, DstClass);
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return {IdReg, GetIdOp};
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}
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// Insert ASSIGN_TYPE instuction between Reg and its definition, set NewReg as
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// a dst of the definition, assign SPIRVType to both registers. If SpirvTy is
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// provided, use it as SPIRVType in ASSIGN_TYPE, otherwise create it from Ty.
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// It's used also in SPIRVBuiltins.cpp.
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// TODO: maybe move to SPIRVUtils.
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namespace llvm {
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Register insertAssignInstr(Register Reg, Type *Ty, SPIRVType *SpirvTy,
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SPIRVGlobalRegistry *GR, MachineIRBuilder &MIB,
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MachineRegisterInfo &MRI) {
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MachineInstr *Def = MRI.getVRegDef(Reg);
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assert((Ty || SpirvTy) && "Either LLVM or SPIRV type is expected.");
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MIB.setInsertPt(*Def->getParent(),
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(Def->getNextNode() ? Def->getNextNode()->getIterator()
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: Def->getParent()->end()));
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Register NewReg = MRI.createGenericVirtualRegister(MRI.getType(Reg));
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if (auto *RC = MRI.getRegClassOrNull(Reg)) {
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MRI.setRegClass(NewReg, RC);
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} else {
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MRI.setRegClass(NewReg, &SPIRV::IDRegClass);
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MRI.setRegClass(Reg, &SPIRV::IDRegClass);
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}
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SpirvTy = SpirvTy ? SpirvTy : GR->getOrCreateSPIRVType(Ty, MIB);
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GR->assignSPIRVTypeToVReg(SpirvTy, Reg, MIB.getMF());
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// This is to make it convenient for Legalizer to get the SPIRVType
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// when processing the actual MI (i.e. not pseudo one).
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GR->assignSPIRVTypeToVReg(SpirvTy, NewReg, MIB.getMF());
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// Copy MIFlags from Def to ASSIGN_TYPE instruction. It's required to keep
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// the flags after instruction selection.
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const uint32_t Flags = Def->getFlags();
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MIB.buildInstr(SPIRV::ASSIGN_TYPE)
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.addDef(Reg)
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.addUse(NewReg)
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.addUse(GR->getSPIRVTypeID(SpirvTy))
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.setMIFlags(Flags);
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Def->getOperand(0).setReg(NewReg);
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return NewReg;
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}
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void processInstr(MachineInstr &MI, MachineIRBuilder &MIB,
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MachineRegisterInfo &MRI, SPIRVGlobalRegistry *GR) {
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unsigned Opc = MI.getOpcode();
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assert(MI.getNumDefs() > 0 && MRI.hasOneUse(MI.getOperand(0).getReg()));
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MachineInstr &AssignTypeInst =
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*(MRI.use_instr_begin(MI.getOperand(0).getReg()));
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auto NewReg = createNewIdReg(MI.getOperand(0).getReg(), Opc, MRI, *GR).first;
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AssignTypeInst.getOperand(1).setReg(NewReg);
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MI.getOperand(0).setReg(NewReg);
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MIB.setInsertPt(*MI.getParent(),
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(MI.getNextNode() ? MI.getNextNode()->getIterator()
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: MI.getParent()->end()));
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for (auto &Op : MI.operands()) {
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if (!Op.isReg() || Op.isDef())
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continue;
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auto IdOpInfo = createNewIdReg(Op.getReg(), Opc, MRI, *GR);
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MIB.buildInstr(IdOpInfo.second).addDef(IdOpInfo.first).addUse(Op.getReg());
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Op.setReg(IdOpInfo.first);
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}
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}
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} // namespace llvm
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static void generateAssignInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR,
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MachineIRBuilder MIB) {
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// Get access to information about available extensions
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const SPIRVSubtarget *ST =
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static_cast<const SPIRVSubtarget *>(&MIB.getMF().getSubtarget());
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MachineRegisterInfo &MRI = MF.getRegInfo();
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SmallVector<MachineInstr *, 10> ToErase;
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for (MachineBasicBlock *MBB : post_order(&MF)) {
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if (MBB->empty())
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continue;
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bool ReachedBegin = false;
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for (auto MII = std::prev(MBB->end()), Begin = MBB->begin();
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!ReachedBegin;) {
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MachineInstr &MI = *MII;
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if (isSpvIntrinsic(MI, Intrinsic::spv_assign_ptr_type)) {
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Register Reg = MI.getOperand(1).getReg();
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MIB.setInsertPt(*MI.getParent(), MI.getIterator());
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SPIRVType *BaseTy = GR->getOrCreateSPIRVType(
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getMDOperandAsType(MI.getOperand(2).getMetadata(), 0), MIB);
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SPIRVType *AssignedPtrType = GR->getOrCreateSPIRVPointerType(
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BaseTy, MI, *MF.getSubtarget<SPIRVSubtarget>().getInstrInfo(),
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addressSpaceToStorageClass(MI.getOperand(3).getImm(), *ST));
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MachineInstr *Def = MRI.getVRegDef(Reg);
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assert(Def && "Expecting an instruction that defines the register");
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// G_GLOBAL_VALUE already has type info.
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if (Def->getOpcode() != TargetOpcode::G_GLOBAL_VALUE)
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insertAssignInstr(Reg, nullptr, AssignedPtrType, GR, MIB,
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MF.getRegInfo());
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ToErase.push_back(&MI);
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} else if (isSpvIntrinsic(MI, Intrinsic::spv_assign_type)) {
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Register Reg = MI.getOperand(1).getReg();
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Type *Ty = getMDOperandAsType(MI.getOperand(2).getMetadata(), 0);
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MachineInstr *Def = MRI.getVRegDef(Reg);
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assert(Def && "Expecting an instruction that defines the register");
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// G_GLOBAL_VALUE already has type info.
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if (Def->getOpcode() != TargetOpcode::G_GLOBAL_VALUE)
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insertAssignInstr(Reg, Ty, nullptr, GR, MIB, MF.getRegInfo());
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ToErase.push_back(&MI);
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} else if (MI.getOpcode() == TargetOpcode::G_CONSTANT ||
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MI.getOpcode() == TargetOpcode::G_FCONSTANT ||
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MI.getOpcode() == TargetOpcode::G_BUILD_VECTOR) {
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// %rc = G_CONSTANT ty Val
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// ===>
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// %cty = OpType* ty
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// %rctmp = G_CONSTANT ty Val
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// %rc = ASSIGN_TYPE %rctmp, %cty
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Register Reg = MI.getOperand(0).getReg();
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if (MRI.hasOneUse(Reg)) {
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MachineInstr &UseMI = *MRI.use_instr_begin(Reg);
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if (isSpvIntrinsic(UseMI, Intrinsic::spv_assign_type) ||
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isSpvIntrinsic(UseMI, Intrinsic::spv_assign_name))
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continue;
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}
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Type *Ty = nullptr;
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if (MI.getOpcode() == TargetOpcode::G_CONSTANT)
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Ty = MI.getOperand(1).getCImm()->getType();
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else if (MI.getOpcode() == TargetOpcode::G_FCONSTANT)
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Ty = MI.getOperand(1).getFPImm()->getType();
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else {
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assert(MI.getOpcode() == TargetOpcode::G_BUILD_VECTOR);
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Type *ElemTy = nullptr;
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MachineInstr *ElemMI = MRI.getVRegDef(MI.getOperand(1).getReg());
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assert(ElemMI);
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if (ElemMI->getOpcode() == TargetOpcode::G_CONSTANT)
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ElemTy = ElemMI->getOperand(1).getCImm()->getType();
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else if (ElemMI->getOpcode() == TargetOpcode::G_FCONSTANT)
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ElemTy = ElemMI->getOperand(1).getFPImm()->getType();
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else
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llvm_unreachable("Unexpected opcode");
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unsigned NumElts =
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MI.getNumExplicitOperands() - MI.getNumExplicitDefs();
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Ty = VectorType::get(ElemTy, NumElts, false);
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}
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insertAssignInstr(Reg, Ty, nullptr, GR, MIB, MRI);
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} else if (MI.getOpcode() == TargetOpcode::G_TRUNC ||
|
|
MI.getOpcode() == TargetOpcode::G_GLOBAL_VALUE ||
|
|
MI.getOpcode() == TargetOpcode::COPY ||
|
|
MI.getOpcode() == TargetOpcode::G_ADDRSPACE_CAST) {
|
|
propagateSPIRVType(&MI, GR, MRI, MIB);
|
|
}
|
|
|
|
if (MII == Begin)
|
|
ReachedBegin = true;
|
|
else
|
|
--MII;
|
|
}
|
|
}
|
|
for (MachineInstr *MI : ToErase)
|
|
MI->eraseFromParent();
|
|
}
|
|
|
|
// Defined in SPIRVLegalizerInfo.cpp.
|
|
extern bool isTypeFoldingSupported(unsigned Opcode);
|
|
|
|
static void processInstrsWithTypeFolding(MachineFunction &MF,
|
|
SPIRVGlobalRegistry *GR,
|
|
MachineIRBuilder MIB) {
|
|
MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
for (MachineBasicBlock &MBB : MF) {
|
|
for (MachineInstr &MI : MBB) {
|
|
if (isTypeFoldingSupported(MI.getOpcode()))
|
|
processInstr(MI, MIB, MRI, GR);
|
|
}
|
|
}
|
|
for (MachineBasicBlock &MBB : MF) {
|
|
for (MachineInstr &MI : MBB) {
|
|
// We need to rewrite dst types for ASSIGN_TYPE instrs to be able
|
|
// to perform tblgen'erated selection and we can't do that on Legalizer
|
|
// as it operates on gMIR only.
|
|
if (MI.getOpcode() != SPIRV::ASSIGN_TYPE)
|
|
continue;
|
|
Register SrcReg = MI.getOperand(1).getReg();
|
|
unsigned Opcode = MRI.getVRegDef(SrcReg)->getOpcode();
|
|
if (!isTypeFoldingSupported(Opcode))
|
|
continue;
|
|
Register DstReg = MI.getOperand(0).getReg();
|
|
if (MRI.getType(DstReg).isVector())
|
|
MRI.setRegClass(DstReg, &SPIRV::IDRegClass);
|
|
// Don't need to reset type of register holding constant and used in
|
|
// G_ADDRSPACE_CAST, since it braaks legalizer.
|
|
if (Opcode == TargetOpcode::G_CONSTANT && MRI.hasOneUse(DstReg)) {
|
|
MachineInstr &UseMI = *MRI.use_instr_begin(DstReg);
|
|
if (UseMI.getOpcode() == TargetOpcode::G_ADDRSPACE_CAST)
|
|
continue;
|
|
}
|
|
MRI.setType(DstReg, LLT::scalar(32));
|
|
}
|
|
}
|
|
}
|
|
|
|
// Find basic blocks of the switch and replace registers in spv_switch() by its
|
|
// MBB equivalent.
|
|
static void processSwitches(MachineFunction &MF, SPIRVGlobalRegistry *GR,
|
|
MachineIRBuilder MIB) {
|
|
DenseMap<const BasicBlock *, MachineBasicBlock *> BB2MBB;
|
|
SmallVector<std::pair<MachineInstr *, SmallVector<MachineInstr *, 8>>>
|
|
Switches;
|
|
for (MachineBasicBlock &MBB : MF) {
|
|
MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
BB2MBB[MBB.getBasicBlock()] = &MBB;
|
|
for (MachineInstr &MI : MBB) {
|
|
if (!isSpvIntrinsic(MI, Intrinsic::spv_switch))
|
|
continue;
|
|
// Calls to spv_switch intrinsics representing IR switches.
|
|
SmallVector<MachineInstr *, 8> NewOps;
|
|
for (unsigned i = 2; i < MI.getNumOperands(); ++i) {
|
|
Register Reg = MI.getOperand(i).getReg();
|
|
if (i % 2 == 1) {
|
|
MachineInstr *ConstInstr = getDefInstrMaybeConstant(Reg, &MRI);
|
|
NewOps.push_back(ConstInstr);
|
|
} else {
|
|
MachineInstr *BuildMBB = MRI.getVRegDef(Reg);
|
|
assert(BuildMBB &&
|
|
BuildMBB->getOpcode() == TargetOpcode::G_BLOCK_ADDR &&
|
|
BuildMBB->getOperand(1).isBlockAddress() &&
|
|
BuildMBB->getOperand(1).getBlockAddress());
|
|
NewOps.push_back(BuildMBB);
|
|
}
|
|
}
|
|
Switches.push_back(std::make_pair(&MI, NewOps));
|
|
}
|
|
}
|
|
|
|
SmallPtrSet<MachineInstr *, 8> ToEraseMI;
|
|
for (auto &SwIt : Switches) {
|
|
MachineInstr &MI = *SwIt.first;
|
|
SmallVector<MachineInstr *, 8> &Ins = SwIt.second;
|
|
SmallVector<MachineOperand, 8> NewOps;
|
|
for (unsigned i = 0; i < Ins.size(); ++i) {
|
|
if (Ins[i]->getOpcode() == TargetOpcode::G_BLOCK_ADDR) {
|
|
BasicBlock *CaseBB =
|
|
Ins[i]->getOperand(1).getBlockAddress()->getBasicBlock();
|
|
auto It = BB2MBB.find(CaseBB);
|
|
if (It == BB2MBB.end())
|
|
report_fatal_error("cannot find a machine basic block by a basic "
|
|
"block in a switch statement");
|
|
NewOps.push_back(MachineOperand::CreateMBB(It->second));
|
|
MI.getParent()->addSuccessor(It->second);
|
|
ToEraseMI.insert(Ins[i]);
|
|
} else {
|
|
NewOps.push_back(
|
|
MachineOperand::CreateCImm(Ins[i]->getOperand(1).getCImm()));
|
|
}
|
|
}
|
|
for (unsigned i = MI.getNumOperands() - 1; i > 1; --i)
|
|
MI.removeOperand(i);
|
|
for (auto &MO : NewOps)
|
|
MI.addOperand(MO);
|
|
if (MachineInstr *Next = MI.getNextNode()) {
|
|
if (isSpvIntrinsic(*Next, Intrinsic::spv_track_constant)) {
|
|
ToEraseMI.insert(Next);
|
|
Next = MI.getNextNode();
|
|
}
|
|
if (Next && Next->getOpcode() == TargetOpcode::G_BRINDIRECT)
|
|
ToEraseMI.insert(Next);
|
|
}
|
|
}
|
|
for (MachineInstr *BlockAddrI : ToEraseMI)
|
|
BlockAddrI->eraseFromParent();
|
|
}
|
|
|
|
static bool isImplicitFallthrough(MachineBasicBlock &MBB) {
|
|
if (MBB.empty())
|
|
return true;
|
|
|
|
// Branching SPIR-V intrinsics are not detected by this generic method.
|
|
// Thus, we can only trust negative result.
|
|
if (!MBB.canFallThrough())
|
|
return false;
|
|
|
|
// Otherwise, we must manually check if we have a SPIR-V intrinsic which
|
|
// prevent an implicit fallthrough.
|
|
for (MachineBasicBlock::reverse_iterator It = MBB.rbegin(), E = MBB.rend();
|
|
It != E; ++It) {
|
|
if (isSpvIntrinsic(*It, Intrinsic::spv_switch))
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
static void removeImplicitFallthroughs(MachineFunction &MF,
|
|
MachineIRBuilder MIB) {
|
|
// It is valid for MachineBasicBlocks to not finish with a branch instruction.
|
|
// In such cases, they will simply fallthrough their immediate successor.
|
|
for (MachineBasicBlock &MBB : MF) {
|
|
if (!isImplicitFallthrough(MBB))
|
|
continue;
|
|
|
|
assert(std::distance(MBB.successors().begin(), MBB.successors().end()) ==
|
|
1);
|
|
MIB.setInsertPt(MBB, MBB.end());
|
|
MIB.buildBr(**MBB.successors().begin());
|
|
}
|
|
}
|
|
|
|
bool SPIRVPreLegalizer::runOnMachineFunction(MachineFunction &MF) {
|
|
// Initialize the type registry.
|
|
const SPIRVSubtarget &ST = MF.getSubtarget<SPIRVSubtarget>();
|
|
SPIRVGlobalRegistry *GR = ST.getSPIRVGlobalRegistry();
|
|
GR->setCurrentFunc(MF);
|
|
MachineIRBuilder MIB(MF);
|
|
addConstantsToTrack(MF, GR);
|
|
foldConstantsIntoIntrinsics(MF);
|
|
insertBitcasts(MF, GR, MIB);
|
|
generateAssignInstrs(MF, GR, MIB);
|
|
processSwitches(MF, GR, MIB);
|
|
processInstrsWithTypeFolding(MF, GR, MIB);
|
|
removeImplicitFallthroughs(MF, MIB);
|
|
|
|
return true;
|
|
}
|
|
|
|
INITIALIZE_PASS(SPIRVPreLegalizer, DEBUG_TYPE, "SPIRV pre legalizer", false,
|
|
false)
|
|
|
|
char SPIRVPreLegalizer::ID = 0;
|
|
|
|
FunctionPass *llvm::createSPIRVPreLegalizerPass() {
|
|
return new SPIRVPreLegalizer();
|
|
}
|