db158c7c83
Refresh of the generic scheduling model to use A510 instead of A55. Main benefits are to the little core, and introducing SVE scheduling information. Changes tested on various OoO cores, no performance degradation is seen. Differential Revision: https://reviews.llvm.org/D156799
231 lines
8.4 KiB
LLVM
231 lines
8.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
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; Odd divisor
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define <4 x i32> @test_srem_odd_25(<4 x i32> %X) nounwind {
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; CHECK-LABEL: test_srem_odd_25:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #23593 // =0x5c29
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; CHECK-NEXT: mov w9, #47185 // =0xb851
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; CHECK-NEXT: movk w8, #49807, lsl #16
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; CHECK-NEXT: movk w9, #1310, lsl #16
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; CHECK-NEXT: dup v1.4s, w8
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; CHECK-NEXT: dup v2.4s, w9
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; CHECK-NEXT: mov w8, #28834 // =0x70a2
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; CHECK-NEXT: movk w8, #2621, lsl #16
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; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
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; CHECK-NEXT: dup v0.4s, w8
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; CHECK-NEXT: movi v1.4s, #1
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; CHECK-NEXT: cmhs v0.4s, v0.4s, v2.4s
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; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%srem = srem <4 x i32> %X, <i32 25, i32 25, i32 25, i32 25>
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%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
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%ret = zext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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; Even divisors
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define <4 x i32> @test_srem_even_100(<4 x i32> %X) nounwind {
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; CHECK-LABEL: test_srem_even_100:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #23593 // =0x5c29
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; CHECK-NEXT: mov w9, #47184 // =0xb850
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; CHECK-NEXT: movk w8, #49807, lsl #16
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; CHECK-NEXT: movk w9, #1310, lsl #16
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; CHECK-NEXT: dup v1.4s, w8
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; CHECK-NEXT: dup v2.4s, w9
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; CHECK-NEXT: mov w8, #23592 // =0x5c28
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; CHECK-NEXT: movk w8, #655, lsl #16
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; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
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; CHECK-NEXT: dup v1.4s, w8
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; CHECK-NEXT: shl v0.4s, v2.4s, #30
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; CHECK-NEXT: usra v0.4s, v2.4s, #2
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; CHECK-NEXT: movi v2.4s, #1
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; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
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; CHECK-NEXT: ret
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%srem = srem <4 x i32> %X, <i32 100, i32 100, i32 100, i32 100>
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%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
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%ret = zext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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; Negative divisors should be negated, and thus this is still splat vectors.
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; Odd divisor
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define <4 x i32> @test_srem_odd_neg25(<4 x i32> %X) nounwind {
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; CHECK-LABEL: test_srem_odd_neg25:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #23593 // =0x5c29
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; CHECK-NEXT: mov w9, #47185 // =0xb851
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; CHECK-NEXT: movk w8, #49807, lsl #16
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; CHECK-NEXT: movk w9, #1310, lsl #16
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; CHECK-NEXT: dup v1.4s, w8
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; CHECK-NEXT: dup v2.4s, w9
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; CHECK-NEXT: mov w8, #28834 // =0x70a2
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; CHECK-NEXT: movk w8, #2621, lsl #16
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; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
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; CHECK-NEXT: dup v0.4s, w8
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; CHECK-NEXT: movi v1.4s, #1
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; CHECK-NEXT: cmhs v0.4s, v0.4s, v2.4s
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; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%srem = srem <4 x i32> %X, <i32 25, i32 -25, i32 -25, i32 25>
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%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
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%ret = zext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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; Even divisors
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define <4 x i32> @test_srem_even_neg100(<4 x i32> %X) nounwind {
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; CHECK-LABEL: test_srem_even_neg100:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #23593 // =0x5c29
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; CHECK-NEXT: mov w9, #47184 // =0xb850
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; CHECK-NEXT: movk w8, #49807, lsl #16
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; CHECK-NEXT: movk w9, #1310, lsl #16
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; CHECK-NEXT: dup v1.4s, w8
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; CHECK-NEXT: dup v2.4s, w9
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; CHECK-NEXT: mov w8, #23592 // =0x5c28
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; CHECK-NEXT: movk w8, #655, lsl #16
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; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
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; CHECK-NEXT: dup v1.4s, w8
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; CHECK-NEXT: shl v0.4s, v2.4s, #30
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; CHECK-NEXT: usra v0.4s, v2.4s, #2
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; CHECK-NEXT: movi v2.4s, #1
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; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
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; CHECK-NEXT: ret
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%srem = srem <4 x i32> %X, <i32 -100, i32 100, i32 -100, i32 100>
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%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
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%ret = zext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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;------------------------------------------------------------------------------;
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; Comparison constant has undef elements.
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;------------------------------------------------------------------------------;
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define <4 x i32> @test_srem_odd_undef1(<4 x i32> %X) nounwind {
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; CHECK-LABEL: test_srem_odd_undef1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #34079 // =0x851f
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; CHECK-NEXT: movk w8, #20971, lsl #16
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; CHECK-NEXT: dup v1.4s, w8
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; CHECK-NEXT: smull2 v2.2d, v0.4s, v1.4s
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; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
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; CHECK-NEXT: uzp2 v1.4s, v1.4s, v2.4s
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; CHECK-NEXT: sshr v2.4s, v1.4s, #3
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; CHECK-NEXT: usra v2.4s, v1.4s, #31
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; CHECK-NEXT: movi v1.4s, #25
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; CHECK-NEXT: mls v0.4s, v2.4s, v1.4s
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; CHECK-NEXT: movi v1.4s, #1
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; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
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; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%srem = srem <4 x i32> %X, <i32 25, i32 25, i32 25, i32 25>
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%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 undef, i32 0>
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%ret = zext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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define <4 x i32> @test_srem_even_undef1(<4 x i32> %X) nounwind {
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; CHECK-LABEL: test_srem_even_undef1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #34079 // =0x851f
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; CHECK-NEXT: movk w8, #20971, lsl #16
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; CHECK-NEXT: dup v1.4s, w8
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; CHECK-NEXT: smull2 v2.2d, v0.4s, v1.4s
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; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
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; CHECK-NEXT: uzp2 v1.4s, v1.4s, v2.4s
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; CHECK-NEXT: sshr v2.4s, v1.4s, #5
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; CHECK-NEXT: usra v2.4s, v1.4s, #31
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; CHECK-NEXT: movi v1.4s, #100
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; CHECK-NEXT: mls v0.4s, v2.4s, v1.4s
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; CHECK-NEXT: movi v1.4s, #1
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; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
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; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%srem = srem <4 x i32> %X, <i32 100, i32 100, i32 100, i32 100>
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%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 undef, i32 0>
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%ret = zext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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;------------------------------------------------------------------------------;
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; Negative tests
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;------------------------------------------------------------------------------;
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define <4 x i32> @test_srem_one_eq(<4 x i32> %X) nounwind {
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; CHECK-LABEL: test_srem_one_eq:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v0.4s, #1
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; CHECK-NEXT: ret
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%srem = srem <4 x i32> %X, <i32 1, i32 1, i32 1, i32 1>
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%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
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%ret = zext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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define <4 x i32> @test_srem_one_ne(<4 x i32> %X) nounwind {
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; CHECK-LABEL: test_srem_one_ne:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v0.2d, #0000000000000000
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; CHECK-NEXT: ret
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%srem = srem <4 x i32> %X, <i32 1, i32 1, i32 1, i32 1>
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%cmp = icmp ne <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
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%ret = zext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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; We can lower remainder of division by powers of two much better elsewhere.
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define <4 x i32> @test_srem_pow2(<4 x i32> %X) nounwind {
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; CHECK-LABEL: test_srem_pow2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmlt v1.4s, v0.4s, #0
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; CHECK-NEXT: mov v2.16b, v0.16b
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; CHECK-NEXT: usra v2.4s, v1.4s, #28
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; CHECK-NEXT: movi v1.4s, #1
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; CHECK-NEXT: bic v2.4s, #15
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; CHECK-NEXT: sub v0.4s, v0.4s, v2.4s
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; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
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; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%srem = srem <4 x i32> %X, <i32 16, i32 16, i32 16, i32 16>
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%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
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%ret = zext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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; We could lower remainder of division by INT_MIN much better elsewhere.
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define <4 x i32> @test_srem_int_min(<4 x i32> %X) nounwind {
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; CHECK-LABEL: test_srem_int_min:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmlt v1.4s, v0.4s, #0
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; CHECK-NEXT: mov v2.16b, v0.16b
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; CHECK-NEXT: usra v2.4s, v1.4s, #1
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; CHECK-NEXT: movi v1.4s, #128, lsl #24
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; CHECK-NEXT: and v1.16b, v2.16b, v1.16b
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; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: movi v1.4s, #1
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; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
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; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%srem = srem <4 x i32> %X, <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>
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%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
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%ret = zext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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; We could lower remainder of division by all-ones much better elsewhere.
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define <4 x i32> @test_srem_allones(<4 x i32> %X) nounwind {
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; CHECK-LABEL: test_srem_allones:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v0.4s, #1
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; CHECK-NEXT: ret
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%srem = srem <4 x i32> %X, <i32 4294967295, i32 4294967295, i32 4294967295, i32 4294967295>
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%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
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%ret = zext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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