b24af43fdf
By default the scheduling info of instructions into a BUNDLE are given a latency of 0 as they operate on the implicit register of the bundle. This modifies that for AArch64 so that the latency is adjusted to use the latency from the instruction in the bundle instead. This essentially assumes that the bundled instructions are executed in a single cycle, which for AArch64 is probably OK considering they are mostly used for MOVPFX bundles, where this can help create slightly better scheduling especially for in-order cores.
55 lines
2.1 KiB
LLVM
55 lines
2.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64 -mattr=+sve,+dotprod < %s | FileCheck %s
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define i32 @test(<vscale x 32 x i8> %bin.rdx, <vscale x 32 x i8> %bin.rdx2) {
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; CHECK-LABEL: test:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sunpklo z4.h, z2.b
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; CHECK-NEXT: sunpklo z5.h, z0.b
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; CHECK-NEXT: sunpkhi z0.h, z0.b
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; CHECK-NEXT: sunpkhi z2.h, z2.b
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: sunpklo z6.h, z1.b
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; CHECK-NEXT: sunpkhi z1.h, z1.b
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; CHECK-NEXT: sunpklo z7.h, z3.b
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; CHECK-NEXT: sunpkhi z3.h, z3.b
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; CHECK-NEXT: sunpkhi z24.s, z5.h
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; CHECK-NEXT: sunpklo z5.s, z5.h
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; CHECK-NEXT: sunpklo z25.s, z4.h
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; CHECK-NEXT: sunpklo z26.s, z0.h
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; CHECK-NEXT: sunpkhi z4.s, z4.h
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; CHECK-NEXT: sunpklo z27.s, z2.h
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; CHECK-NEXT: sunpkhi z0.s, z0.h
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; CHECK-NEXT: sunpkhi z2.s, z2.h
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; CHECK-NEXT: sunpklo z28.s, z6.h
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; CHECK-NEXT: sunpkhi z6.s, z6.h
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; CHECK-NEXT: mul z5.s, p0/m, z5.s, z25.s
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; CHECK-NEXT: sunpkhi z25.s, z1.h
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; CHECK-NEXT: sunpklo z1.s, z1.h
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; CHECK-NEXT: mul z26.s, p0/m, z26.s, z27.s
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; CHECK-NEXT: mul z4.s, p0/m, z4.s, z24.s
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; CHECK-NEXT: sunpkhi z24.s, z3.h
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; CHECK-NEXT: mul z0.s, p0/m, z0.s, z2.s
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; CHECK-NEXT: sunpkhi z2.s, z7.h
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; CHECK-NEXT: sunpklo z7.s, z7.h
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; CHECK-NEXT: sunpklo z3.s, z3.h
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; CHECK-NEXT: mla z0.s, p0/m, z25.s, z24.s
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; CHECK-NEXT: mad z2.s, p0/m, z6.s, z4.s
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; CHECK-NEXT: mad z1.s, p0/m, z3.s, z26.s
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; CHECK-NEXT: movprfx z3, z5
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; CHECK-NEXT: mla z3.s, p0/m, z28.s, z7.s
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; CHECK-NEXT: add z0.s, z2.s, z0.s
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; CHECK-NEXT: add z1.s, z3.s, z1.s
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; CHECK-NEXT: add z0.s, z1.s, z0.s
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; CHECK-NEXT: uaddv d0, p0, z0.s
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; CHECK-NEXT: fmov x0, d0
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; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
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; CHECK-NEXT: ret
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%a = sext <vscale x 32 x i8> %bin.rdx to <vscale x 32 x i32>
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%b = sext <vscale x 32 x i8> %bin.rdx2 to <vscale x 32 x i32>
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%c = mul <vscale x 32 x i32> %a, %b
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%r = call i32 @llvm.vector.reduce.add.nxv32i32(<vscale x 32 x i32> %c)
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ret i32 %r
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}
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declare i32 @llvm.vector.reduce.add.nxv32i32(<vscale x 32 x i32> )
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