e1472db58e
There's a target hook that's called in DAGCombiner that we stub here, I'll
implement the equivalent override for AArch64 in a subsequent patch since it's
used by different shift combine.
This change by itself has minor code size improvements on arm64 -Os CTMark:
Program size.__text
outputg181ppyy output8av1cxfn diff
consumer-typeset/consumer-typeset 410648.00 410648.00 0.0%
tramp3d-v4/tramp3d-v4 364176.00 364176.00 0.0%
kimwitu++/kc 449216.00 449212.00 -0.0%
7zip/7zip-benchmark 576128.00 576120.00 -0.0%
sqlite3/sqlite3 285108.00 285100.00 -0.0%
SPASS/SPASS 411720.00 411688.00 -0.0%
ClamAV/clamscan 379868.00 379764.00 -0.0%
Bullet/bullet 452064.00 451928.00 -0.0%
mafft/pairlocalalign 246184.00 246108.00 -0.0%
lencod/lencod 428524.00 428152.00 -0.1%
Geomean difference -0.0%
Differential Revision: https://reviews.llvm.org/D150086
146 lines
4.8 KiB
LLVM
146 lines
4.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=VI %s
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; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 %s
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; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
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; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
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; ===================================================================================
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; V_ADD_LSHL_U32
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; ===================================================================================
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define amdgpu_ps float @add_shl(i32 %a, i32 %b, i32 %c) {
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; VI-LABEL: add_shl:
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; VI: ; %bb.0:
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; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1
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; VI-NEXT: v_lshlrev_b32_e32 v0, v2, v0
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: add_shl:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_add_lshl_u32 v0, v0, v1, v2
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: add_shl:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_add_lshl_u32 v0, v0, v1, v2
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; GFX10-NEXT: ; return to shader part epilog
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%x = add i32 %a, %b
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%result = shl i32 %x, %c
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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define amdgpu_ps float @add_shl_vgpr_c(i32 inreg %a, i32 inreg %b, i32 %c) {
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; VI-LABEL: add_shl_vgpr_c:
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; VI: ; %bb.0:
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; VI-NEXT: s_add_i32 s2, s2, s3
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; VI-NEXT: v_lshlrev_b32_e64 v0, v0, s2
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: add_shl_vgpr_c:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_add_i32 s2, s2, s3
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; GFX9-NEXT: v_lshlrev_b32_e64 v0, v0, s2
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: add_shl_vgpr_c:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_add_i32 s2, s2, s3
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; GFX10-NEXT: v_lshlrev_b32_e64 v0, v0, s2
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; GFX10-NEXT: ; return to shader part epilog
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%x = add i32 %a, %b
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%result = shl i32 %x, %c
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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define amdgpu_ps float @add_shl_vgpr_ac(i32 %a, i32 inreg %b, i32 %c) {
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; VI-LABEL: add_shl_vgpr_ac:
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; VI: ; %bb.0:
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; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
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; VI-NEXT: v_lshlrev_b32_e32 v0, v1, v0
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: add_shl_vgpr_ac:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_add_lshl_u32 v0, v0, s2, v1
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: add_shl_vgpr_ac:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_add_lshl_u32 v0, v0, s2, v1
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; GFX10-NEXT: ; return to shader part epilog
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%x = add i32 %a, %b
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%result = shl i32 %x, %c
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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define amdgpu_ps float @add_shl_vgpr_const(i32 %a, i32 %b) {
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; VI-LABEL: add_shl_vgpr_const:
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; VI: ; %bb.0:
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; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1
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; VI-NEXT: v_lshlrev_b32_e32 v0, 9, v0
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: add_shl_vgpr_const:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_add_lshl_u32 v0, v0, v1, 9
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: add_shl_vgpr_const:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_add_lshl_u32 v0, v0, v1, 9
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; GFX10-NEXT: ; return to shader part epilog
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%x = add i32 %a, %b
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%result = shl i32 %x, 9
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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define amdgpu_ps float @add_shl_vgpr_const_inline_const(i32 %a) {
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; VI-LABEL: add_shl_vgpr_const_inline_const:
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; VI: ; %bb.0:
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; VI-NEXT: v_lshlrev_b32_e32 v0, 9, v0
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; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7e800, v0
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: add_shl_vgpr_const_inline_const:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_mov_b32_e32 v1, 0x7e800
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; GFX9-NEXT: v_lshl_add_u32 v0, v0, 9, v1
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: add_shl_vgpr_const_inline_const:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_lshl_add_u32 v0, v0, 9, 0x7e800
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; GFX10-NEXT: ; return to shader part epilog
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%x = add i32 %a, 1012
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%result = shl i32 %x, 9
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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define amdgpu_ps float @add_shl_vgpr_inline_const_x2(i32 %a) {
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; VI-LABEL: add_shl_vgpr_inline_const_x2:
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; VI: ; %bb.0:
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; VI-NEXT: v_lshlrev_b32_e32 v0, 9, v0
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; VI-NEXT: v_add_u32_e32 v0, vcc, 0x600, v0
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: add_shl_vgpr_inline_const_x2:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_mov_b32_e32 v1, 0x600
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; GFX9-NEXT: v_lshl_add_u32 v0, v0, 9, v1
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: add_shl_vgpr_inline_const_x2:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_lshl_add_u32 v0, v0, 9, 0x600
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; GFX10-NEXT: ; return to shader part epilog
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%x = add i32 %a, 3
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%result = shl i32 %x, 9
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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