9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
432 lines
18 KiB
YAML
432 lines
18 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX6 %s
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# RUN: llc -mtriple=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX7 %s
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# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX8 %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX9 %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX10 %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX10 %s
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---
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name: ashr_s32_ss
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; GFX6-LABEL: name: ashr_s32_ss
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; GFX6: liveins: $sgpr0, $sgpr1
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; GFX6-NEXT: {{ $}}
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; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GFX6-NEXT: [[S_ASHR_I32_:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[COPY]], [[COPY1]], implicit-def dead $scc
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; GFX6-NEXT: S_ENDPGM 0, implicit [[S_ASHR_I32_]]
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;
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; GFX7-LABEL: name: ashr_s32_ss
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; GFX7: liveins: $sgpr0, $sgpr1
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; GFX7-NEXT: {{ $}}
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; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GFX7-NEXT: [[S_ASHR_I32_:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[COPY]], [[COPY1]], implicit-def dead $scc
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; GFX7-NEXT: S_ENDPGM 0, implicit [[S_ASHR_I32_]]
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;
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; GFX8-LABEL: name: ashr_s32_ss
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; GFX8: liveins: $sgpr0, $sgpr1
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; GFX8-NEXT: {{ $}}
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; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GFX8-NEXT: [[S_ASHR_I32_:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[COPY]], [[COPY1]], implicit-def dead $scc
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; GFX8-NEXT: S_ENDPGM 0, implicit [[S_ASHR_I32_]]
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;
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; GFX9-LABEL: name: ashr_s32_ss
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; GFX9: liveins: $sgpr0, $sgpr1
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; GFX9-NEXT: {{ $}}
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; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GFX9-NEXT: [[S_ASHR_I32_:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[COPY]], [[COPY1]], implicit-def dead $scc
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; GFX9-NEXT: S_ENDPGM 0, implicit [[S_ASHR_I32_]]
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;
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; GFX10-LABEL: name: ashr_s32_ss
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; GFX10: liveins: $sgpr0, $sgpr1
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; GFX10-NEXT: {{ $}}
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; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GFX10-NEXT: [[S_ASHR_I32_:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[COPY]], [[COPY1]], implicit-def dead $scc
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; GFX10-NEXT: S_ENDPGM 0, implicit [[S_ASHR_I32_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = COPY $sgpr1
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%2:sgpr(s32) = G_ASHR %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: ashr_s32_sv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; GFX6-LABEL: name: ashr_s32_sv
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; GFX6: liveins: $sgpr0, $vgpr0
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; GFX6-NEXT: {{ $}}
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; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX6-NEXT: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
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; GFX6-NEXT: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
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;
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; GFX7-LABEL: name: ashr_s32_sv
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; GFX7: liveins: $sgpr0, $vgpr0
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; GFX7-NEXT: {{ $}}
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; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX7-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX7-NEXT: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
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; GFX7-NEXT: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
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;
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; GFX8-LABEL: name: ashr_s32_sv
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; GFX8: liveins: $sgpr0, $vgpr0
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; GFX8-NEXT: {{ $}}
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; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX8-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX8-NEXT: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
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; GFX8-NEXT: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
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;
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; GFX9-LABEL: name: ashr_s32_sv
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; GFX9: liveins: $sgpr0, $vgpr0
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; GFX9-NEXT: {{ $}}
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; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX9-NEXT: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
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; GFX9-NEXT: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
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;
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; GFX10-LABEL: name: ashr_s32_sv
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; GFX10: liveins: $sgpr0, $vgpr0
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; GFX10-NEXT: {{ $}}
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; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX10-NEXT: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
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; GFX10-NEXT: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = COPY $vgpr0
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%2:vgpr(s32) = G_ASHR %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: ashr_s32_vs
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; GFX6-LABEL: name: ashr_s32_vs
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; GFX6: liveins: $sgpr0, $vgpr0
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; GFX6-NEXT: {{ $}}
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; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX6-NEXT: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
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; GFX6-NEXT: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
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;
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; GFX7-LABEL: name: ashr_s32_vs
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; GFX7: liveins: $sgpr0, $vgpr0
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; GFX7-NEXT: {{ $}}
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; GFX7-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX7-NEXT: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
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; GFX7-NEXT: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
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;
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; GFX8-LABEL: name: ashr_s32_vs
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; GFX8: liveins: $sgpr0, $vgpr0
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; GFX8-NEXT: {{ $}}
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; GFX8-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX8-NEXT: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
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; GFX8-NEXT: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
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;
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; GFX9-LABEL: name: ashr_s32_vs
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; GFX9: liveins: $sgpr0, $vgpr0
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; GFX9-NEXT: {{ $}}
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; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX9-NEXT: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
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; GFX9-NEXT: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
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;
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; GFX10-LABEL: name: ashr_s32_vs
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; GFX10: liveins: $sgpr0, $vgpr0
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; GFX10-NEXT: {{ $}}
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; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX10-NEXT: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
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; GFX10-NEXT: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr(s32) = COPY $sgpr0
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%2:vgpr(s32) = G_ASHR %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: ashr_s32_vv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX6-LABEL: name: ashr_s32_vv
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; GFX6: liveins: $vgpr0, $vgpr1
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; GFX6-NEXT: {{ $}}
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; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX6-NEXT: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
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; GFX6-NEXT: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
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;
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; GFX7-LABEL: name: ashr_s32_vv
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; GFX7: liveins: $vgpr0, $vgpr1
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; GFX7-NEXT: {{ $}}
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; GFX7-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX7-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX7-NEXT: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
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; GFX7-NEXT: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
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;
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; GFX8-LABEL: name: ashr_s32_vv
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; GFX8: liveins: $vgpr0, $vgpr1
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; GFX8-NEXT: {{ $}}
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; GFX8-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX8-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX8-NEXT: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
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; GFX8-NEXT: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
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;
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; GFX9-LABEL: name: ashr_s32_vv
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; GFX9: liveins: $vgpr0, $vgpr1
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; GFX9-NEXT: {{ $}}
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; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX9-NEXT: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
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; GFX9-NEXT: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
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;
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; GFX10-LABEL: name: ashr_s32_vv
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; GFX10: liveins: $vgpr0, $vgpr1
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; GFX10-NEXT: {{ $}}
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; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX10-NEXT: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
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; GFX10-NEXT: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s32) = G_ASHR %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: ashr_s64_ss
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $sgpr2
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; GFX6-LABEL: name: ashr_s64_ss
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; GFX6: liveins: $sgpr0_sgpr1, $sgpr2
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; GFX6-NEXT: {{ $}}
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; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
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; GFX6-NEXT: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 [[COPY]], [[COPY1]], implicit-def dead $scc
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; GFX6-NEXT: S_ENDPGM 0, implicit [[S_ASHR_I64_]]
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;
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; GFX7-LABEL: name: ashr_s64_ss
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; GFX7: liveins: $sgpr0_sgpr1, $sgpr2
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; GFX7-NEXT: {{ $}}
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; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
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; GFX7-NEXT: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 [[COPY]], [[COPY1]], implicit-def dead $scc
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; GFX7-NEXT: S_ENDPGM 0, implicit [[S_ASHR_I64_]]
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;
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; GFX8-LABEL: name: ashr_s64_ss
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; GFX8: liveins: $sgpr0_sgpr1, $sgpr2
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; GFX8-NEXT: {{ $}}
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; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
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; GFX8-NEXT: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 [[COPY]], [[COPY1]], implicit-def dead $scc
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; GFX8-NEXT: S_ENDPGM 0, implicit [[S_ASHR_I64_]]
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;
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; GFX9-LABEL: name: ashr_s64_ss
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; GFX9: liveins: $sgpr0_sgpr1, $sgpr2
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; GFX9-NEXT: {{ $}}
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; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
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; GFX9-NEXT: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 [[COPY]], [[COPY1]], implicit-def dead $scc
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; GFX9-NEXT: S_ENDPGM 0, implicit [[S_ASHR_I64_]]
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;
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; GFX10-LABEL: name: ashr_s64_ss
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; GFX10: liveins: $sgpr0_sgpr1, $sgpr2
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; GFX10-NEXT: {{ $}}
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; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
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; GFX10-NEXT: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 [[COPY]], [[COPY1]], implicit-def dead $scc
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; GFX10-NEXT: S_ENDPGM 0, implicit [[S_ASHR_I64_]]
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%0:sgpr(s64) = COPY $sgpr0_sgpr1
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%1:sgpr(s32) = COPY $sgpr2
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%2:sgpr(s64) = G_ASHR %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: ashr_s64_sv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $vgpr0
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; GFX6-LABEL: name: ashr_s64_sv
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; GFX6: liveins: $sgpr0_sgpr1, $vgpr0
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; GFX6-NEXT: {{ $}}
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; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
|
; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
; GFX6-NEXT: [[V_ASHR_I64_e64_:%[0-9]+]]:vreg_64 = V_ASHR_I64_e64 [[COPY]], [[COPY1]], implicit $exec
|
|
; GFX6-NEXT: S_ENDPGM 0, implicit [[V_ASHR_I64_e64_]]
|
|
;
|
|
; GFX7-LABEL: name: ashr_s64_sv
|
|
; GFX7: liveins: $sgpr0_sgpr1, $vgpr0
|
|
; GFX7-NEXT: {{ $}}
|
|
; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
|
; GFX7-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
; GFX7-NEXT: [[V_ASHR_I64_e64_:%[0-9]+]]:vreg_64 = V_ASHR_I64_e64 [[COPY]], [[COPY1]], implicit $exec
|
|
; GFX7-NEXT: S_ENDPGM 0, implicit [[V_ASHR_I64_e64_]]
|
|
;
|
|
; GFX8-LABEL: name: ashr_s64_sv
|
|
; GFX8: liveins: $sgpr0_sgpr1, $vgpr0
|
|
; GFX8-NEXT: {{ $}}
|
|
; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
|
; GFX8-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
; GFX8-NEXT: [[V_ASHRREV_I64_e64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64_e64 [[COPY1]], [[COPY]], implicit $exec
|
|
; GFX8-NEXT: S_ENDPGM 0, implicit [[V_ASHRREV_I64_e64_]]
|
|
;
|
|
; GFX9-LABEL: name: ashr_s64_sv
|
|
; GFX9: liveins: $sgpr0_sgpr1, $vgpr0
|
|
; GFX9-NEXT: {{ $}}
|
|
; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
|
; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
; GFX9-NEXT: [[V_ASHRREV_I64_e64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64_e64 [[COPY1]], [[COPY]], implicit $exec
|
|
; GFX9-NEXT: S_ENDPGM 0, implicit [[V_ASHRREV_I64_e64_]]
|
|
;
|
|
; GFX10-LABEL: name: ashr_s64_sv
|
|
; GFX10: liveins: $sgpr0_sgpr1, $vgpr0
|
|
; GFX10-NEXT: {{ $}}
|
|
; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
|
; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
; GFX10-NEXT: [[V_ASHRREV_I64_e64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64_e64 [[COPY1]], [[COPY]], implicit $exec
|
|
; GFX10-NEXT: S_ENDPGM 0, implicit [[V_ASHRREV_I64_e64_]]
|
|
%0:sgpr(s64) = COPY $sgpr0_sgpr1
|
|
%1:vgpr(s32) = COPY $vgpr0
|
|
%2:vgpr(s64) = G_ASHR %0, %1
|
|
S_ENDPGM 0, implicit %2
|
|
...
|
|
|
|
---
|
|
name: ashr_s64_vs
|
|
legalized: true
|
|
regBankSelected: true
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $sgpr0, $vgpr0_vgpr1
|
|
; GFX6-LABEL: name: ashr_s64_vs
|
|
; GFX6: liveins: $sgpr0, $vgpr0_vgpr1
|
|
; GFX6-NEXT: {{ $}}
|
|
; GFX6-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
|
; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
|
; GFX6-NEXT: [[V_ASHR_I64_e64_:%[0-9]+]]:vreg_64 = V_ASHR_I64_e64 [[COPY]], [[COPY1]], implicit $exec
|
|
; GFX6-NEXT: S_ENDPGM 0, implicit [[V_ASHR_I64_e64_]]
|
|
;
|
|
; GFX7-LABEL: name: ashr_s64_vs
|
|
; GFX7: liveins: $sgpr0, $vgpr0_vgpr1
|
|
; GFX7-NEXT: {{ $}}
|
|
; GFX7-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
|
; GFX7-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
|
; GFX7-NEXT: [[V_ASHR_I64_e64_:%[0-9]+]]:vreg_64 = V_ASHR_I64_e64 [[COPY]], [[COPY1]], implicit $exec
|
|
; GFX7-NEXT: S_ENDPGM 0, implicit [[V_ASHR_I64_e64_]]
|
|
;
|
|
; GFX8-LABEL: name: ashr_s64_vs
|
|
; GFX8: liveins: $sgpr0, $vgpr0_vgpr1
|
|
; GFX8-NEXT: {{ $}}
|
|
; GFX8-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
|
; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
|
; GFX8-NEXT: [[V_ASHRREV_I64_e64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64_e64 [[COPY1]], [[COPY]], implicit $exec
|
|
; GFX8-NEXT: S_ENDPGM 0, implicit [[V_ASHRREV_I64_e64_]]
|
|
;
|
|
; GFX9-LABEL: name: ashr_s64_vs
|
|
; GFX9: liveins: $sgpr0, $vgpr0_vgpr1
|
|
; GFX9-NEXT: {{ $}}
|
|
; GFX9-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
|
; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
|
; GFX9-NEXT: [[V_ASHRREV_I64_e64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64_e64 [[COPY1]], [[COPY]], implicit $exec
|
|
; GFX9-NEXT: S_ENDPGM 0, implicit [[V_ASHRREV_I64_e64_]]
|
|
;
|
|
; GFX10-LABEL: name: ashr_s64_vs
|
|
; GFX10: liveins: $sgpr0, $vgpr0_vgpr1
|
|
; GFX10-NEXT: {{ $}}
|
|
; GFX10-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
|
; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
|
; GFX10-NEXT: [[V_ASHRREV_I64_e64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64_e64 [[COPY1]], [[COPY]], implicit $exec
|
|
; GFX10-NEXT: S_ENDPGM 0, implicit [[V_ASHRREV_I64_e64_]]
|
|
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
|
%1:sgpr(s32) = COPY $sgpr0
|
|
%2:vgpr(s64) = G_ASHR %0, %1
|
|
S_ENDPGM 0, implicit %2
|
|
...
|
|
|
|
---
|
|
name: ashr_s64_vv
|
|
legalized: true
|
|
regBankSelected: true
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr0_vgpr1, $vgpr2
|
|
; GFX6-LABEL: name: ashr_s64_vv
|
|
; GFX6: liveins: $vgpr0_vgpr1, $vgpr2
|
|
; GFX6-NEXT: {{ $}}
|
|
; GFX6-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
|
; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
|
; GFX6-NEXT: [[V_ASHR_I64_e64_:%[0-9]+]]:vreg_64 = V_ASHR_I64_e64 [[COPY]], [[COPY1]], implicit $exec
|
|
; GFX6-NEXT: S_ENDPGM 0, implicit [[V_ASHR_I64_e64_]]
|
|
;
|
|
; GFX7-LABEL: name: ashr_s64_vv
|
|
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2
|
|
; GFX7-NEXT: {{ $}}
|
|
; GFX7-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
|
; GFX7-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
|
; GFX7-NEXT: [[V_ASHR_I64_e64_:%[0-9]+]]:vreg_64 = V_ASHR_I64_e64 [[COPY]], [[COPY1]], implicit $exec
|
|
; GFX7-NEXT: S_ENDPGM 0, implicit [[V_ASHR_I64_e64_]]
|
|
;
|
|
; GFX8-LABEL: name: ashr_s64_vv
|
|
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2
|
|
; GFX8-NEXT: {{ $}}
|
|
; GFX8-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
|
; GFX8-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
|
; GFX8-NEXT: [[V_ASHRREV_I64_e64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64_e64 [[COPY1]], [[COPY]], implicit $exec
|
|
; GFX8-NEXT: S_ENDPGM 0, implicit [[V_ASHRREV_I64_e64_]]
|
|
;
|
|
; GFX9-LABEL: name: ashr_s64_vv
|
|
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
|
|
; GFX9-NEXT: {{ $}}
|
|
; GFX9-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
|
; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
|
; GFX9-NEXT: [[V_ASHRREV_I64_e64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64_e64 [[COPY1]], [[COPY]], implicit $exec
|
|
; GFX9-NEXT: S_ENDPGM 0, implicit [[V_ASHRREV_I64_e64_]]
|
|
;
|
|
; GFX10-LABEL: name: ashr_s64_vv
|
|
; GFX10: liveins: $vgpr0_vgpr1, $vgpr2
|
|
; GFX10-NEXT: {{ $}}
|
|
; GFX10-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
|
; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
|
; GFX10-NEXT: [[V_ASHRREV_I64_e64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64_e64 [[COPY1]], [[COPY]], implicit $exec
|
|
; GFX10-NEXT: S_ENDPGM 0, implicit [[V_ASHRREV_I64_e64_]]
|
|
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
|
%1:vgpr(s32) = COPY $vgpr2
|
|
%2:vgpr(s64) = G_ASHR %0, %1
|
|
S_ENDPGM 0, implicit %2
|
|
...
|