9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
49 lines
1.6 KiB
LLVM
49 lines
1.6 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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declare i16 @llvm.amdgcn.frexp.exp.i16.f16(half %a)
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; GCN-LABEL: {{^}}frexp_exp_f16
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; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
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; VI: v_frexp_exp_i16_f16_e32 v[[R_I16:[0-9]+]], v[[A_F16]]
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; GCN: buffer_store_short v[[R_I16]]
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define amdgpu_kernel void @frexp_exp_f16(
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ptr addrspace(1) %r,
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ptr addrspace(1) %a) {
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entry:
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%a.val = load half, ptr addrspace(1) %a
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%r.val = call i16 @llvm.amdgcn.frexp.exp.i16.f16(half %a.val)
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store i16 %r.val, ptr addrspace(1) %r
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ret void
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}
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; GCN-LABEL: {{^}}frexp_exp_f16_sext
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; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
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; VI: v_frexp_exp_i16_f16_e32 v[[R_I16:[0-9]+]], v[[A_F16]]
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; VI: v_bfe_i32 v[[R_I32:[0-9]+]], v[[R_I16]], 0, 16{{$}}
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; GCN: buffer_store_dword v[[R_I32]]
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define amdgpu_kernel void @frexp_exp_f16_sext(
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ptr addrspace(1) %r,
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ptr addrspace(1) %a) {
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entry:
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%a.val = load half, ptr addrspace(1) %a
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%r.val = call i16 @llvm.amdgcn.frexp.exp.i16.f16(half %a.val)
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%r.val.sext = sext i16 %r.val to i32
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store i32 %r.val.sext, ptr addrspace(1) %r
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ret void
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}
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; GCN-LABEL: {{^}}frexp_exp_f16_zext
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; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
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; VI: v_frexp_exp_i16_f16_e32 v[[R_I16:[0-9]+]], v[[A_F16]]
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; GCN: buffer_store_dword v[[R_I16]]
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define amdgpu_kernel void @frexp_exp_f16_zext(
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ptr addrspace(1) %r,
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ptr addrspace(1) %a) {
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entry:
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%a.val = load half, ptr addrspace(1) %a
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%r.val = call i16 @llvm.amdgcn.frexp.exp.i16.f16(half %a.val)
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%r.val.zext = zext i16 %r.val to i32
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store i32 %r.val.zext, ptr addrspace(1) %r
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ret void
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}
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