9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
30 lines
1.2 KiB
LLVM
30 lines
1.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; This test used to crash
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define amdgpu_ps float @xor3_i1_const(float inreg %arg1, i32 inreg %arg2) {
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; GCN-LABEL: xor3_i1_const:
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; GCN: ; %bb.0: ; %main_body
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; GCN-NEXT: v_mov_b32_e32 v0, 0x42640000
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; GCN-NEXT: v_cmp_lt_f32_e64 s[2:3], s0, 0
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; GCN-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
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; GCN-NEXT: s_and_b64 s[0:1], s[2:3], vcc
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; GCN-NEXT: v_cndmask_b32_e64 v0, 1.0, 0, s[0:1]
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; GCN-NEXT: ; return to shader part epilog
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main_body:
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%tmp26 = fcmp nsz olt float %arg1, 0.000000e+00
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%tmp28 = call nsz float @llvm.amdgcn.interp.p2(float undef, float undef, i32 0, i32 0, i32 %arg2)
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%tmp29 = fcmp nsz olt float %arg1, 5.700000e+01
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%tmp31 = fcmp nsz olt float %tmp28, 0.000000e+00
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%.demorgan = and i1 %tmp26, %tmp29
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%tmp34 = xor i1 %.demorgan, true
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%tmp35 = and i1 %tmp31, %tmp34
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%tmp36 = xor i1 %tmp35, true
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%tmp37 = xor i1 %.demorgan, %tmp36
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%tmp42 = or i1 %tmp37, %tmp35
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%tmp43 = select i1 %tmp42, float 1.000000e+00, float 0.000000e+00
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ret float %tmp43
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}
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declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32)
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