0ec51a460a
DAGCombiner replaces (load const_addr1) directly chained with (store (val, const_addr2)) with val if address space stripped const_addr1 == const_addr2. The patch fixes the issue by checking address spaces as well. However, it might makes sense to not to chain together side effects that belong to different address spaces in the first place and make SelectionDAG::root address space aware.
22 lines
673 B
LLVM
22 lines
673 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=nvptx64 < %s | FileCheck %s
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define i64 @test() nounwind readnone {
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; CHECK-LABEL: test(
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; CHECK: {
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; CHECK-NEXT: .reg .b64 %rd<4>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: mov.u64 %rd1, 1;
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; CHECK-NEXT: mov.u64 %rd2, 42;
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; CHECK-NEXT: st.u64 [%rd1], %rd2;
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; CHECK-NEXT: ld.global.u64 %rd3, [%rd1];
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; CHECK-NEXT: st.param.b64 [func_retval0+0], %rd3;
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; CHECK-NEXT: ret;
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%addr0 = inttoptr i64 1 to ptr
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%addr1 = inttoptr i64 1 to ptr addrspace(1)
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store i64 42, ptr %addr0
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%res = load i64, ptr addrspace(1) %addr1
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ret i64 %res
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}
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