llvm-project

History

[InterleavedAccessPass] Get round the unsupported large scalarize vectors (#88643 )

When build with option -msve-vector-bits=512, the return vaule of
Subtarget->getMinSVEVectorSizeInBits() is 512;
While the MinElts is still 4 for <vscale x 4 x double> in
getNumInterleavedAccesses, so it creates invalid
llvm.aarch64.sve.ld2.sret.nxv4f64, which need be splited.
Unlikely, the related custom spilting is not supported now.

Fix https://github.com/llvm/llvm-project/issues/88247

2024-04-16 09:00:03 +08:00

AArch64

[InterleavedAccessPass] Get round the unsupported large scalarize vectors (#88643 )

2024-04-16 09:00:03 +08:00

ARM

[CodeGen] Port InterleavedAccess to new pass manager (#74904 )

2023-12-10 19:15:51 +08:00

RISCV

[RISCV] Remove blank lines at the end of testcases. NFC.

2024-01-02 13:13:04 +08:00

X86

[CodeGen] Port InterleavedAccess to new pass manager (#74904 )

2023-12-10 19:15:51 +08:00