b1c4b55118
Attempt to only define used subregisters when creating IMPLICIT_DEF fix ups for live interval subranges. This avoids the appearance at the MIR level of entire (wide) registers becoming live rather than relying only on transient LiveIntervals dead definitions for unused subregisters.
455 lines
17 KiB
C++
455 lines
17 KiB
C++
//===-- RenameIndependentSubregs.cpp - Live Interval Analysis -------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// Rename independent subregisters looks for virtual registers with
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/// independently used subregisters and renames them to new virtual registers.
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/// Example: In the following:
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/// %0:sub0<read-undef> = ...
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/// %0:sub1 = ...
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/// use %0:sub0
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/// %0:sub0 = ...
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/// use %0:sub0
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/// use %0:sub1
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/// sub0 and sub1 are never used together, and we have two independent sub0
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/// definitions. This pass will rename to:
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/// %0:sub0<read-undef> = ...
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/// %1:sub1<read-undef> = ...
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/// use %1:sub1
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/// %2:sub1<read-undef> = ...
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/// use %2:sub1
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/// use %0:sub0
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/RenameIndependentSubregs.h"
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#include "LiveRangeUtils.h"
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#include "PHIEliminationUtils.h"
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#include "llvm/CodeGen/LiveInterval.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/InitializePasses.h"
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#include "llvm/Pass.h"
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using namespace llvm;
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#define DEBUG_TYPE "rename-independent-subregs"
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namespace {
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class RenameIndependentSubregs {
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public:
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RenameIndependentSubregs(LiveIntervals *LIS) : LIS(LIS) {}
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bool run(MachineFunction &MF);
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private:
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struct SubRangeInfo {
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ConnectedVNInfoEqClasses ConEQ;
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LiveInterval::SubRange *SR;
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unsigned Index;
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SubRangeInfo(LiveIntervals &LIS, LiveInterval::SubRange &SR,
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unsigned Index)
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: ConEQ(LIS), SR(&SR), Index(Index) {}
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};
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/// Split unrelated subregister components and rename them to new vregs.
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bool renameComponents(LiveInterval &LI) const;
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/// Build a vector of SubRange infos and a union find set of
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/// equivalence classes.
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/// Returns true if more than 1 equivalence class was found.
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bool findComponents(IntEqClasses &Classes,
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SmallVectorImpl<SubRangeInfo> &SubRangeInfos,
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LiveInterval &LI) const;
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/// Distribute the LiveInterval segments into the new LiveIntervals
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/// belonging to their class.
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void distribute(const IntEqClasses &Classes,
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const SmallVectorImpl<SubRangeInfo> &SubRangeInfos,
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const SmallVectorImpl<LiveInterval*> &Intervals) const;
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/// Constructs main liverange and add missing undef+dead flags.
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void computeMainRangesFixFlags(const IntEqClasses &Classes,
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const SmallVectorImpl<SubRangeInfo> &SubRangeInfos,
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const SmallVectorImpl<LiveInterval*> &Intervals) const;
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/// Rewrite Machine Operands to use the new vreg belonging to their class.
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void rewriteOperands(const IntEqClasses &Classes,
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const SmallVectorImpl<SubRangeInfo> &SubRangeInfos,
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const SmallVectorImpl<LiveInterval*> &Intervals) const;
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LiveIntervals *LIS = nullptr;
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MachineRegisterInfo *MRI = nullptr;
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const TargetInstrInfo *TII = nullptr;
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};
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class RenameIndependentSubregsLegacy : public MachineFunctionPass {
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public:
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static char ID;
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RenameIndependentSubregsLegacy() : MachineFunctionPass(ID) {}
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override {
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return "Rename Disconnected Subregister Components";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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AU.addRequired<LiveIntervalsWrapperPass>();
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AU.addPreserved<LiveIntervalsWrapperPass>();
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AU.addRequired<SlotIndexesWrapperPass>();
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AU.addPreserved<SlotIndexesWrapperPass>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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} // end anonymous namespace
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char RenameIndependentSubregsLegacy::ID;
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char &llvm::RenameIndependentSubregsID = RenameIndependentSubregsLegacy::ID;
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INITIALIZE_PASS_BEGIN(RenameIndependentSubregsLegacy, DEBUG_TYPE,
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"Rename Independent Subregisters", false, false)
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INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
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INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
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INITIALIZE_PASS_END(RenameIndependentSubregsLegacy, DEBUG_TYPE,
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"Rename Independent Subregisters", false, false)
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bool RenameIndependentSubregs::renameComponents(LiveInterval &LI) const {
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// Shortcut: We cannot have split components with a single definition.
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if (LI.valnos.size() < 2)
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return false;
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SmallVector<SubRangeInfo, 4> SubRangeInfos;
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IntEqClasses Classes;
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if (!findComponents(Classes, SubRangeInfos, LI))
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return false;
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// Create a new VReg for each class.
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Register Reg = LI.reg();
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const TargetRegisterClass *RegClass = MRI->getRegClass(Reg);
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SmallVector<LiveInterval*, 4> Intervals;
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Intervals.push_back(&LI);
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LLVM_DEBUG(dbgs() << printReg(Reg) << ": Found " << Classes.getNumClasses()
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<< " equivalence classes.\n");
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LLVM_DEBUG(dbgs() << printReg(Reg) << ": Splitting into newly created:");
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for (unsigned I = 1, NumClasses = Classes.getNumClasses(); I < NumClasses;
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++I) {
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Register NewVReg = MRI->createVirtualRegister(RegClass);
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LiveInterval &NewLI = LIS->createEmptyInterval(NewVReg);
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Intervals.push_back(&NewLI);
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LLVM_DEBUG(dbgs() << ' ' << printReg(NewVReg));
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}
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LLVM_DEBUG(dbgs() << '\n');
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rewriteOperands(Classes, SubRangeInfos, Intervals);
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distribute(Classes, SubRangeInfos, Intervals);
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computeMainRangesFixFlags(Classes, SubRangeInfos, Intervals);
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return true;
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}
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bool RenameIndependentSubregs::findComponents(IntEqClasses &Classes,
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SmallVectorImpl<RenameIndependentSubregs::SubRangeInfo> &SubRangeInfos,
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LiveInterval &LI) const {
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// First step: Create connected components for the VNInfos inside the
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// subranges and count the global number of such components.
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unsigned NumComponents = 0;
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for (LiveInterval::SubRange &SR : LI.subranges()) {
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SubRangeInfos.push_back(SubRangeInfo(*LIS, SR, NumComponents));
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ConnectedVNInfoEqClasses &ConEQ = SubRangeInfos.back().ConEQ;
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unsigned NumSubComponents = ConEQ.Classify(SR);
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NumComponents += NumSubComponents;
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}
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// Shortcut: With only 1 subrange, the normal separate component tests are
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// enough and we do not need to perform the union-find on the subregister
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// segments.
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if (SubRangeInfos.size() < 2)
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return false;
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// Next step: Build union-find structure over all subranges and merge classes
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// across subranges when they are affected by the same MachineOperand.
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const TargetRegisterInfo &TRI = *MRI->getTargetRegisterInfo();
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Classes.grow(NumComponents);
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Register Reg = LI.reg();
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for (const MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) {
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if (!MO.isDef() && !MO.readsReg())
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continue;
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unsigned SubRegIdx = MO.getSubReg();
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LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx);
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unsigned MergedID = ~0u;
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for (RenameIndependentSubregs::SubRangeInfo &SRInfo : SubRangeInfos) {
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const LiveInterval::SubRange &SR = *SRInfo.SR;
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if ((SR.LaneMask & LaneMask).none())
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continue;
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SlotIndex Pos = LIS->getInstructionIndex(*MO.getParent());
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Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber())
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: Pos.getBaseIndex();
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const VNInfo *VNI = SR.getVNInfoAt(Pos);
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if (VNI == nullptr)
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continue;
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// Map to local representant ID.
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unsigned LocalID = SRInfo.ConEQ.getEqClass(VNI);
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// Global ID
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unsigned ID = LocalID + SRInfo.Index;
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// Merge other sets
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MergedID = MergedID == ~0u ? ID : Classes.join(MergedID, ID);
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}
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}
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// Early exit if we ended up with a single equivalence class.
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Classes.compress();
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unsigned NumClasses = Classes.getNumClasses();
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return NumClasses > 1;
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}
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void RenameIndependentSubregs::rewriteOperands(const IntEqClasses &Classes,
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const SmallVectorImpl<SubRangeInfo> &SubRangeInfos,
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const SmallVectorImpl<LiveInterval*> &Intervals) const {
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const TargetRegisterInfo &TRI = *MRI->getTargetRegisterInfo();
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Register Reg = Intervals[0]->reg();
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for (MachineRegisterInfo::reg_nodbg_iterator I = MRI->reg_nodbg_begin(Reg),
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E = MRI->reg_nodbg_end(); I != E; ) {
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MachineOperand &MO = *I++;
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if (!MO.isDef() && !MO.readsReg())
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continue;
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auto *MI = MO.getParent();
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SlotIndex Pos = LIS->getInstructionIndex(*MI);
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Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber())
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: Pos.getBaseIndex();
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unsigned SubRegIdx = MO.getSubReg();
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LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx);
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unsigned ID = ~0u;
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for (const SubRangeInfo &SRInfo : SubRangeInfos) {
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const LiveInterval::SubRange &SR = *SRInfo.SR;
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if ((SR.LaneMask & LaneMask).none())
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continue;
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const VNInfo *VNI = SR.getVNInfoAt(Pos);
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if (VNI == nullptr)
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continue;
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// Map to local representant ID.
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unsigned LocalID = SRInfo.ConEQ.getEqClass(VNI);
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// Global ID
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ID = Classes[LocalID + SRInfo.Index];
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break;
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}
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Register VReg = Intervals[ID]->reg();
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MO.setReg(VReg);
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if (MO.isTied() && Reg != VReg) {
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/// Undef use operands are not tracked in the equivalence class,
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/// but need to be updated if they are tied; take care to only
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/// update the tied operand.
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unsigned OperandNo = MO.getOperandNo();
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unsigned TiedIdx = MI->findTiedOperandIdx(OperandNo);
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MI->getOperand(TiedIdx).setReg(VReg);
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// above substitution breaks the iterator, so restart.
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I = MRI->reg_nodbg_begin(Reg);
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}
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}
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// TODO: We could attempt to recompute new register classes while visiting
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// the operands: Some of the split register may be fine with less constraint
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// classes than the original vreg.
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}
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void RenameIndependentSubregs::distribute(const IntEqClasses &Classes,
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const SmallVectorImpl<SubRangeInfo> &SubRangeInfos,
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const SmallVectorImpl<LiveInterval*> &Intervals) const {
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unsigned NumClasses = Classes.getNumClasses();
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SmallVector<unsigned, 8> VNIMapping;
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SmallVector<LiveInterval::SubRange*, 8> SubRanges;
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BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator();
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for (const SubRangeInfo &SRInfo : SubRangeInfos) {
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LiveInterval::SubRange &SR = *SRInfo.SR;
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unsigned NumValNos = SR.valnos.size();
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VNIMapping.clear();
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VNIMapping.reserve(NumValNos);
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SubRanges.clear();
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SubRanges.resize(NumClasses-1, nullptr);
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for (unsigned I = 0; I < NumValNos; ++I) {
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const VNInfo &VNI = *SR.valnos[I];
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unsigned LocalID = SRInfo.ConEQ.getEqClass(&VNI);
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unsigned ID = Classes[LocalID + SRInfo.Index];
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VNIMapping.push_back(ID);
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if (ID > 0 && SubRanges[ID-1] == nullptr)
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SubRanges[ID-1] = Intervals[ID]->createSubRange(Allocator, SR.LaneMask);
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}
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DistributeRange(SR, SubRanges.data(), VNIMapping);
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}
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}
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static bool subRangeLiveAt(const LiveInterval &LI, SlotIndex Pos) {
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for (const LiveInterval::SubRange &SR : LI.subranges()) {
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if (SR.liveAt(Pos))
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return true;
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}
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return false;
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}
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void RenameIndependentSubregs::computeMainRangesFixFlags(
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const IntEqClasses &Classes,
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const SmallVectorImpl<SubRangeInfo> &SubRangeInfos,
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const SmallVectorImpl<LiveInterval*> &Intervals) const {
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const TargetRegisterInfo &TRI = TII->getRegisterInfo();
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BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator();
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const SlotIndexes &Indexes = *LIS->getSlotIndexes();
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for (size_t I = 0, E = Intervals.size(); I < E; ++I) {
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LiveInterval &LI = *Intervals[I];
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Register Reg = LI.reg();
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LI.removeEmptySubRanges();
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// Try to establish a single subregister which covers all uses.
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// Note: this is assuming the selected subregister will only be
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// used for fixing up live intervals issues created by this pass.
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LaneBitmask UsedMask, UnusedMask;
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for (LiveInterval::SubRange &SR : LI.subranges())
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UsedMask |= SR.LaneMask;
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SmallVector<unsigned> SubRegIdxs;
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unsigned Flags = 0;
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unsigned SubReg = 0;
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// TODO: Handle SubRegIdxs.size() > 1
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if (TRI.getCoveringSubRegIndexes(MRI->getRegClass(Reg), UsedMask,
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SubRegIdxs) &&
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SubRegIdxs.size() == 1) {
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SubReg = SubRegIdxs.front();
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Flags = RegState::Undef;
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} else {
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UnusedMask = MRI->getMaxLaneMaskForVReg(Reg) & ~UsedMask;
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}
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// There must be a def (or live-in) before every use. Splitting vregs may
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// violate this principle as the splitted vreg may not have a definition on
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// every path. Fix this by creating IMPLICIT_DEF instruction as necessary.
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for (const LiveInterval::SubRange &SR : LI.subranges()) {
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// Search for "PHI" value numbers in the subranges. We must find a live
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// value in each predecessor block, add an IMPLICIT_DEF where it is
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// missing.
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for (unsigned I = 0; I < SR.valnos.size(); ++I) {
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const VNInfo &VNI = *SR.valnos[I];
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if (VNI.isUnused() || !VNI.isPHIDef())
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continue;
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SlotIndex Def = VNI.def;
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MachineBasicBlock &MBB = *Indexes.getMBBFromIndex(Def);
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for (MachineBasicBlock *PredMBB : MBB.predecessors()) {
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SlotIndex PredEnd = Indexes.getMBBEndIdx(PredMBB);
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if (subRangeLiveAt(LI, PredEnd.getPrevSlot()))
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continue;
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MachineBasicBlock::iterator InsertPos =
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llvm::findPHICopyInsertPoint(PredMBB, &MBB, Reg);
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const MCInstrDesc &MCDesc = TII->get(TargetOpcode::IMPLICIT_DEF);
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MachineInstrBuilder ImpDef =
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BuildMI(*PredMBB, InsertPos, DebugLoc(), MCDesc)
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.addDef(Reg, Flags, SubReg);
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SlotIndex DefIdx = LIS->InsertMachineInstrInMaps(*ImpDef);
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SlotIndex RegDefIdx = DefIdx.getRegSlot();
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for (LiveInterval::SubRange &SR : LI.subranges()) {
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VNInfo *SRVNI = SR.getNextValue(RegDefIdx, Allocator);
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SR.addSegment(LiveRange::Segment(RegDefIdx, PredEnd, SRVNI));
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}
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if (!UnusedMask.none()) {
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LiveInterval::SubRange *SR =
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LI.createSubRange(Allocator, UnusedMask);
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SR->createDeadDef(RegDefIdx, Allocator);
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}
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}
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}
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}
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for (MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) {
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if (!MO.isDef())
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continue;
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unsigned SubRegIdx = MO.getSubReg();
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if (SubRegIdx == 0)
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continue;
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// After assigning the new vreg we may not have any other sublanes living
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// in and out of the instruction anymore. We need to add new dead and
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// undef flags in these cases.
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if (!MO.isUndef()) {
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SlotIndex Pos = LIS->getInstructionIndex(*MO.getParent());
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if (!subRangeLiveAt(LI, Pos))
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MO.setIsUndef();
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}
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if (!MO.isDead()) {
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SlotIndex Pos = LIS->getInstructionIndex(*MO.getParent()).getDeadSlot();
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if (!subRangeLiveAt(LI, Pos))
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MO.setIsDead();
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}
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}
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if (I == 0)
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LI.clear();
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LIS->constructMainRangeFromSubranges(LI);
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// A def of a subregister may be a use of other register lanes. Replacing
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// such a def with a def of a different register will eliminate the use,
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// and may cause the recorded live range to be larger than the actual
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// liveness in the program IR.
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LIS->shrinkToUses(&LI);
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}
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}
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PreservedAnalyses
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RenameIndependentSubregsPass::run(MachineFunction &MF,
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MachineFunctionAnalysisManager &MFAM) {
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auto &LIS = MFAM.getResult<LiveIntervalsAnalysis>(MF);
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if (!RenameIndependentSubregs(&LIS).run(MF))
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return PreservedAnalyses::all();
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auto PA = getMachineFunctionPassPreservedAnalyses();
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PA.preserveSet<CFGAnalyses>();
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PA.preserve<LiveIntervalsAnalysis>();
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PA.preserve<SlotIndexesAnalysis>();
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return PA;
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}
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bool RenameIndependentSubregsLegacy::runOnMachineFunction(MachineFunction &MF) {
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auto &LIS = getAnalysis<LiveIntervalsWrapperPass>().getLIS();
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return RenameIndependentSubregs(&LIS).run(MF);
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}
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bool RenameIndependentSubregs::run(MachineFunction &MF) {
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// Skip renaming if liveness of subregister is not tracked.
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MRI = &MF.getRegInfo();
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if (!MRI->subRegLivenessEnabled())
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return false;
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LLVM_DEBUG(dbgs() << "Renaming independent subregister live ranges in "
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<< MF.getName() << '\n');
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TII = MF.getSubtarget().getInstrInfo();
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// Iterate over all vregs. Note that we query getNumVirtRegs() the newly
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// created vregs end up with higher numbers but do not need to be visited as
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// there can't be any further splitting.
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bool Changed = false;
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for (size_t I = 0, E = MRI->getNumVirtRegs(); I < E; ++I) {
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Register Reg = Register::index2VirtReg(I);
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if (!LIS->hasInterval(Reg))
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continue;
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LiveInterval &LI = LIS->getInterval(Reg);
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if (!LI.hasSubRanges())
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continue;
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Changed |= renameComponents(LI);
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}
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return Changed;
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}
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