59da50c771
Context: https://github.com/llvm/llvm-project/pull/171794#discussion_r2614489484 For some reasons, UTC is unable to merge the 'ZVFHMIN' and 'ZVFBFA' CHECK lines in some of the test functions, and emits incorrect CHECK lines for them, once you run UTC again on the file. This hinders the ability to update these tests in bulk, as one has to manually remove the excessed ZVFBFA lines. While I don't know how to fix UTC at this moment, I found a workaround that simply re-orders these two check prefixes. This is effectively a NFC
695 lines
29 KiB
LLVM
695 lines
29 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=ilp32d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN,ZVFH
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; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=ilp32d \
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; RUN: -verify-machineinstrs -early-live-intervals < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN,ZVFH
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; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN,ZVFH
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; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=lp64d \
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; RUN: -verify-machineinstrs -early-live-intervals < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN,ZVFH
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; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m -target-abi=ilp32d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN,ZVFHMIN
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; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m -target-abi=ilp32d \
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; RUN: -verify-machineinstrs -early-live-intervals < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN,ZVFHMIN
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; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+experimental-zvfbfa,+v,+m \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFBFA
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; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+experimental-zvfbfa,+v,+m \
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; RUN: -verify-machineinstrs -early-live-intervals < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFBFA
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define <vscale x 1 x bfloat> @vfmax_nxv1bf16_vv(<vscale x 1 x bfloat> %a, <vscale x 1 x bfloat> %b) {
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; ZVFBFMIN-LABEL: vfmax_nxv1bf16_vv:
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; ZVFBFMIN: # %bb.0:
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; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
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; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v8
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; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
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; ZVFBFMIN-NEXT: vmfeq.vv v0, v10, v10
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; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
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; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v9
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; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
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; ZVFBFMIN-NEXT: vmerge.vvm v9, v10, v8, v0
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; ZVFBFMIN-NEXT: vmfeq.vv v0, v8, v8
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; ZVFBFMIN-NEXT: vmerge.vvm v8, v8, v10, v0
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; ZVFBFMIN-NEXT: vfmax.vv v9, v8, v9
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; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
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; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
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; ZVFBFMIN-NEXT: ret
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;
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; ZVFBFA-LABEL: vfmax_nxv1bf16_vv:
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; ZVFBFA: # %bb.0:
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; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, mf4, ta, ma
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; ZVFBFA-NEXT: vmfeq.vv v0, v8, v8
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; ZVFBFA-NEXT: vmerge.vvm v10, v8, v9, v0
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; ZVFBFA-NEXT: vmfeq.vv v0, v9, v9
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; ZVFBFA-NEXT: vmerge.vvm v8, v9, v8, v0
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; ZVFBFA-NEXT: vfmax.vv v8, v8, v10
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; ZVFBFA-NEXT: ret
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%v = call <vscale x 1 x bfloat> @llvm.maximum.nxv1bf16(<vscale x 1 x bfloat> %a, <vscale x 1 x bfloat> %b)
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ret <vscale x 1 x bfloat> %v
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}
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define <vscale x 2 x bfloat> @vfmax_nxv2bf16_vv(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b) {
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; ZVFBFMIN-LABEL: vfmax_nxv2bf16_vv:
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; ZVFBFMIN: # %bb.0:
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; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
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; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v8
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; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
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; ZVFBFMIN-NEXT: vmfeq.vv v0, v10, v10
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; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
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; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v9
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; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
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; ZVFBFMIN-NEXT: vmerge.vvm v9, v10, v8, v0
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; ZVFBFMIN-NEXT: vmfeq.vv v0, v8, v8
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; ZVFBFMIN-NEXT: vmerge.vvm v8, v8, v10, v0
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; ZVFBFMIN-NEXT: vfmax.vv v9, v8, v9
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; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
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; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
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; ZVFBFMIN-NEXT: ret
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;
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; ZVFBFA-LABEL: vfmax_nxv2bf16_vv:
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; ZVFBFA: # %bb.0:
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; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, mf2, ta, ma
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; ZVFBFA-NEXT: vmfeq.vv v0, v8, v8
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; ZVFBFA-NEXT: vmerge.vvm v10, v8, v9, v0
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; ZVFBFA-NEXT: vmfeq.vv v0, v9, v9
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; ZVFBFA-NEXT: vmerge.vvm v8, v9, v8, v0
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; ZVFBFA-NEXT: vfmax.vv v8, v8, v10
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; ZVFBFA-NEXT: ret
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%v = call <vscale x 2 x bfloat> @llvm.maximum.nxv2bf16(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b)
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ret <vscale x 2 x bfloat> %v
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}
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define <vscale x 4 x bfloat> @vfmax_nxv4bf16_vv(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b) {
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; ZVFBFMIN-LABEL: vfmax_nxv4bf16_vv:
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; ZVFBFMIN: # %bb.0:
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; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
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; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v8
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; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; ZVFBFMIN-NEXT: vmfeq.vv v0, v10, v10
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; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
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; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v12, v9
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; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; ZVFBFMIN-NEXT: vmerge.vvm v8, v10, v12, v0
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; ZVFBFMIN-NEXT: vmfeq.vv v0, v12, v12
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; ZVFBFMIN-NEXT: vmerge.vvm v10, v12, v10, v0
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; ZVFBFMIN-NEXT: vfmax.vv v10, v10, v8
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; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
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; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v10
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; ZVFBFMIN-NEXT: ret
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;
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; ZVFBFA-LABEL: vfmax_nxv4bf16_vv:
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; ZVFBFA: # %bb.0:
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; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, m1, ta, ma
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; ZVFBFA-NEXT: vmfeq.vv v0, v8, v8
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; ZVFBFA-NEXT: vmerge.vvm v10, v8, v9, v0
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; ZVFBFA-NEXT: vmfeq.vv v0, v9, v9
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; ZVFBFA-NEXT: vmerge.vvm v8, v9, v8, v0
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; ZVFBFA-NEXT: vfmax.vv v8, v8, v10
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; ZVFBFA-NEXT: ret
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%v = call <vscale x 4 x bfloat> @llvm.maximum.nxv4bf16(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b)
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ret <vscale x 4 x bfloat> %v
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}
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define <vscale x 8 x bfloat> @vfmax_nxv8bf16_vv(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {
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; ZVFBFMIN-LABEL: vfmax_nxv8bf16_vv:
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; ZVFBFMIN: # %bb.0:
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; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
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; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v12, v8
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; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
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; ZVFBFMIN-NEXT: vmfeq.vv v0, v12, v12
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; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
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; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v10
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; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
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; ZVFBFMIN-NEXT: vmerge.vvm v8, v12, v16, v0
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; ZVFBFMIN-NEXT: vmfeq.vv v0, v16, v16
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; ZVFBFMIN-NEXT: vmerge.vvm v12, v16, v12, v0
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; ZVFBFMIN-NEXT: vfmax.vv v12, v12, v8
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; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
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; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v12
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; ZVFBFMIN-NEXT: ret
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;
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; ZVFBFA-LABEL: vfmax_nxv8bf16_vv:
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; ZVFBFA: # %bb.0:
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; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, m2, ta, ma
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; ZVFBFA-NEXT: vmfeq.vv v0, v8, v8
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; ZVFBFA-NEXT: vmerge.vvm v12, v8, v10, v0
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; ZVFBFA-NEXT: vmfeq.vv v0, v10, v10
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; ZVFBFA-NEXT: vmerge.vvm v8, v10, v8, v0
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; ZVFBFA-NEXT: vfmax.vv v8, v8, v12
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; ZVFBFA-NEXT: ret
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%v = call <vscale x 8 x bfloat> @llvm.maximum.nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)
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ret <vscale x 8 x bfloat> %v
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}
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define <vscale x 16 x bfloat> @vfmax_nxv16bf16_vv(<vscale x 16 x bfloat> %a, <vscale x 16 x bfloat> %b) {
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; ZVFBFMIN-LABEL: vfmax_nxv16bf16_vv:
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; ZVFBFMIN: # %bb.0:
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; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
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; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v12
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; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v24, v8
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; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
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; ZVFBFMIN-NEXT: vmfeq.vv v0, v24, v24
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; ZVFBFMIN-NEXT: vmfeq.vv v7, v16, v16
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; ZVFBFMIN-NEXT: vmerge.vvm v8, v24, v16, v0
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; ZVFBFMIN-NEXT: vmv1r.v v0, v7
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; ZVFBFMIN-NEXT: vmerge.vvm v16, v16, v24, v0
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; ZVFBFMIN-NEXT: vfmax.vv v16, v16, v8
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; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
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; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v16
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; ZVFBFMIN-NEXT: ret
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;
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; ZVFBFA-LABEL: vfmax_nxv16bf16_vv:
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; ZVFBFA: # %bb.0:
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; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, m4, ta, ma
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; ZVFBFA-NEXT: vmfeq.vv v0, v8, v8
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; ZVFBFA-NEXT: vmerge.vvm v16, v8, v12, v0
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; ZVFBFA-NEXT: vmfeq.vv v0, v12, v12
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; ZVFBFA-NEXT: vmerge.vvm v8, v12, v8, v0
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; ZVFBFA-NEXT: vfmax.vv v8, v8, v16
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; ZVFBFA-NEXT: ret
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%v = call <vscale x 16 x bfloat> @llvm.maximum.nxv16bf16(<vscale x 16 x bfloat> %a, <vscale x 16 x bfloat> %b)
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ret <vscale x 16 x bfloat> %v
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}
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define <vscale x 32 x bfloat> @vfmax_nxv32bf16_vv(<vscale x 32 x bfloat> %a, <vscale x 32 x bfloat> %b) nounwind {
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; ZVFBFMIN-LABEL: vfmax_nxv32bf16_vv:
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; ZVFBFMIN: # %bb.0:
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; ZVFBFMIN-NEXT: addi sp, sp, -16
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; ZVFBFMIN-NEXT: csrr a0, vlenb
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; ZVFBFMIN-NEXT: slli a0, a0, 4
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; ZVFBFMIN-NEXT: sub sp, sp, a0
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; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
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; ZVFBFMIN-NEXT: vmv8r.v v0, v16
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; ZVFBFMIN-NEXT: vmv8r.v v24, v8
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; ZVFBFMIN-NEXT: addi a0, sp, 16
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; ZVFBFMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
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; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v0
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; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v24
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; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
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; ZVFBFMIN-NEXT: vmfeq.vv v0, v8, v8
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; ZVFBFMIN-NEXT: vmfeq.vv v3, v16, v16
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; ZVFBFMIN-NEXT: vmerge.vvm v24, v8, v16, v0
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; ZVFBFMIN-NEXT: csrr a0, vlenb
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; ZVFBFMIN-NEXT: slli a0, a0, 3
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; ZVFBFMIN-NEXT: add a0, sp, a0
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; ZVFBFMIN-NEXT: addi a0, a0, 16
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; ZVFBFMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
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; ZVFBFMIN-NEXT: vmv1r.v v0, v3
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; ZVFBFMIN-NEXT: vmerge.vvm v8, v16, v8, v0
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; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
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; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v24, v4
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; ZVFBFMIN-NEXT: csrr a0, vlenb
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; ZVFBFMIN-NEXT: slli a0, a0, 3
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; ZVFBFMIN-NEXT: add a0, sp, a0
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; ZVFBFMIN-NEXT: addi a0, a0, 16
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; ZVFBFMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
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; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
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; ZVFBFMIN-NEXT: vfmax.vv v8, v8, v16
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; ZVFBFMIN-NEXT: csrr a0, vlenb
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; ZVFBFMIN-NEXT: slli a0, a0, 3
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; ZVFBFMIN-NEXT: add a0, sp, a0
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; ZVFBFMIN-NEXT: addi a0, a0, 16
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; ZVFBFMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
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; ZVFBFMIN-NEXT: addi a0, sp, 16
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; ZVFBFMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
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; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
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; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v20
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; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
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; ZVFBFMIN-NEXT: vmfeq.vv v0, v8, v8
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; ZVFBFMIN-NEXT: vmfeq.vv v7, v24, v24
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; ZVFBFMIN-NEXT: vmerge.vvm v16, v8, v24, v0
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; ZVFBFMIN-NEXT: vmv1r.v v0, v7
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; ZVFBFMIN-NEXT: vmerge.vvm v8, v24, v8, v0
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; ZVFBFMIN-NEXT: vfmax.vv v16, v8, v16
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; ZVFBFMIN-NEXT: csrr a0, vlenb
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; ZVFBFMIN-NEXT: slli a0, a0, 3
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; ZVFBFMIN-NEXT: add a0, sp, a0
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; ZVFBFMIN-NEXT: addi a0, a0, 16
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; ZVFBFMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
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; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
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; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v24
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; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v12, v16
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; ZVFBFMIN-NEXT: csrr a0, vlenb
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; ZVFBFMIN-NEXT: slli a0, a0, 4
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; ZVFBFMIN-NEXT: add sp, sp, a0
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; ZVFBFMIN-NEXT: addi sp, sp, 16
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; ZVFBFMIN-NEXT: ret
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;
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; ZVFBFA-LABEL: vfmax_nxv32bf16_vv:
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; ZVFBFA: # %bb.0:
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; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, m8, ta, ma
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; ZVFBFA-NEXT: vmfeq.vv v0, v8, v8
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; ZVFBFA-NEXT: vmfeq.vv v7, v16, v16
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; ZVFBFA-NEXT: vmerge.vvm v24, v8, v16, v0
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; ZVFBFA-NEXT: vmv1r.v v0, v7
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; ZVFBFA-NEXT: vmerge.vvm v8, v16, v8, v0
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; ZVFBFA-NEXT: vfmax.vv v8, v8, v24
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; ZVFBFA-NEXT: ret
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%v = call <vscale x 32 x bfloat> @llvm.maximum.nxv32bf16(<vscale x 32 x bfloat> %a, <vscale x 32 x bfloat> %b)
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ret <vscale x 32 x bfloat> %v
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}
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define <vscale x 1 x half> @vfmax_nxv1f16_vv(<vscale x 1 x half> %a, <vscale x 1 x half> %b) {
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; ZVFH-LABEL: vfmax_nxv1f16_vv:
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; ZVFH: # %bb.0:
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; ZVFH-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
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; ZVFH-NEXT: vmfeq.vv v0, v8, v8
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; ZVFH-NEXT: vmerge.vvm v10, v8, v9, v0
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; ZVFH-NEXT: vmfeq.vv v0, v9, v9
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; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v0
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; ZVFH-NEXT: vfmax.vv v8, v8, v10
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; ZVFH-NEXT: ret
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;
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; ZVFHMIN-LABEL: vfmax_nxv1f16_vv:
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; ZVFHMIN: # %bb.0:
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; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
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; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
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; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
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; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
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; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
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; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
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; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
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; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0
|
|
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
|
|
; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0
|
|
; ZVFHMIN-NEXT: vfmax.vv v9, v8, v9
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = call <vscale x 1 x half> @llvm.maximum.nxv1f16(<vscale x 1 x half> %a, <vscale x 1 x half> %b)
|
|
ret <vscale x 1 x half> %v
|
|
}
|
|
|
|
define <vscale x 2 x half> @vfmax_nxv2f16_vv(<vscale x 2 x half> %a, <vscale x 2 x half> %b) {
|
|
; ZVFH-LABEL: vfmax_nxv2f16_vv:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
|
|
; ZVFH-NEXT: vmfeq.vv v0, v8, v8
|
|
; ZVFH-NEXT: vmerge.vvm v10, v8, v9, v0
|
|
; ZVFH-NEXT: vmfeq.vv v0, v9, v9
|
|
; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v0
|
|
; ZVFH-NEXT: vfmax.vv v8, v8, v10
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vfmax_nxv2f16_vv:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
|
|
; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
|
|
; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0
|
|
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
|
|
; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0
|
|
; ZVFHMIN-NEXT: vfmax.vv v9, v8, v9
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = call <vscale x 2 x half> @llvm.maximum.nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b)
|
|
ret <vscale x 2 x half> %v
|
|
}
|
|
|
|
define <vscale x 4 x half> @vfmax_nxv4f16_vv(<vscale x 4 x half> %a, <vscale x 4 x half> %b) {
|
|
; ZVFH-LABEL: vfmax_nxv4f16_vv:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma
|
|
; ZVFH-NEXT: vmfeq.vv v0, v8, v8
|
|
; ZVFH-NEXT: vmerge.vvm v10, v8, v9, v0
|
|
; ZVFH-NEXT: vmfeq.vv v0, v9, v9
|
|
; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v0
|
|
; ZVFH-NEXT: vfmax.vv v8, v8, v10
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vfmax_nxv4f16_vv:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
|
|
; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
|
|
; ZVFHMIN-NEXT: vmerge.vvm v8, v10, v12, v0
|
|
; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12
|
|
; ZVFHMIN-NEXT: vmerge.vvm v10, v12, v10, v0
|
|
; ZVFHMIN-NEXT: vfmax.vv v10, v10, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = call <vscale x 4 x half> @llvm.maximum.nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b)
|
|
ret <vscale x 4 x half> %v
|
|
}
|
|
|
|
define <vscale x 8 x half> @vfmax_nxv8f16_vv(<vscale x 8 x half> %a, <vscale x 8 x half> %b) {
|
|
; ZVFH-LABEL: vfmax_nxv8f16_vv:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
|
|
; ZVFH-NEXT: vmfeq.vv v0, v8, v8
|
|
; ZVFH-NEXT: vmerge.vvm v12, v8, v10, v0
|
|
; ZVFH-NEXT: vmfeq.vv v0, v10, v10
|
|
; ZVFH-NEXT: vmerge.vvm v8, v10, v8, v0
|
|
; ZVFH-NEXT: vfmax.vv v8, v8, v12
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vfmax_nxv8f16_vv:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v16, v0
|
|
; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16
|
|
; ZVFHMIN-NEXT: vmerge.vvm v12, v16, v12, v0
|
|
; ZVFHMIN-NEXT: vfmax.vv v12, v12, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = call <vscale x 8 x half> @llvm.maximum.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b)
|
|
ret <vscale x 8 x half> %v
|
|
}
|
|
|
|
define <vscale x 16 x half> @vfmax_nxv16f16_vv(<vscale x 16 x half> %a, <vscale x 16 x half> %b) {
|
|
; ZVFH-LABEL: vfmax_nxv16f16_vv:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetvli a0, zero, e16, m4, ta, ma
|
|
; ZVFH-NEXT: vmfeq.vv v0, v8, v8
|
|
; ZVFH-NEXT: vmerge.vvm v16, v8, v12, v0
|
|
; ZVFH-NEXT: vmfeq.vv v0, v12, v12
|
|
; ZVFH-NEXT: vmerge.vvm v8, v12, v8, v0
|
|
; ZVFH-NEXT: vfmax.vv v8, v8, v16
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vfmax_nxv16f16_vv:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vmfeq.vv v0, v24, v24
|
|
; ZVFHMIN-NEXT: vmfeq.vv v7, v16, v16
|
|
; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v16, v0
|
|
; ZVFHMIN-NEXT: vmv1r.v v0, v7
|
|
; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0
|
|
; ZVFHMIN-NEXT: vfmax.vv v16, v16, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = call <vscale x 16 x half> @llvm.maximum.nxv16f16(<vscale x 16 x half> %a, <vscale x 16 x half> %b)
|
|
ret <vscale x 16 x half> %v
|
|
}
|
|
|
|
define <vscale x 32 x half> @vfmax_nxv32f16_vv(<vscale x 32 x half> %a, <vscale x 32 x half> %b) nounwind {
|
|
; ZVFH-LABEL: vfmax_nxv32f16_vv:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetvli a0, zero, e16, m8, ta, ma
|
|
; ZVFH-NEXT: vmfeq.vv v0, v8, v8
|
|
; ZVFH-NEXT: vmfeq.vv v7, v16, v16
|
|
; ZVFH-NEXT: vmerge.vvm v24, v8, v16, v0
|
|
; ZVFH-NEXT: vmv1r.v v0, v7
|
|
; ZVFH-NEXT: vmerge.vvm v8, v16, v8, v0
|
|
; ZVFH-NEXT: vfmax.vv v8, v8, v24
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vfmax_nxv32f16_vv:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: addi sp, sp, -16
|
|
; ZVFHMIN-NEXT: csrr a0, vlenb
|
|
; ZVFHMIN-NEXT: slli a0, a0, 4
|
|
; ZVFHMIN-NEXT: sub sp, sp, a0
|
|
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vmv8r.v v0, v16
|
|
; ZVFHMIN-NEXT: vmv8r.v v24, v8
|
|
; ZVFHMIN-NEXT: addi a0, sp, 16
|
|
; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v0
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
|
|
; ZVFHMIN-NEXT: vmfeq.vv v3, v16, v16
|
|
; ZVFHMIN-NEXT: vmerge.vvm v24, v8, v16, v0
|
|
; ZVFHMIN-NEXT: csrr a0, vlenb
|
|
; ZVFHMIN-NEXT: slli a0, a0, 3
|
|
; ZVFHMIN-NEXT: add a0, sp, a0
|
|
; ZVFHMIN-NEXT: addi a0, a0, 16
|
|
; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
|
|
; ZVFHMIN-NEXT: vmv1r.v v0, v3
|
|
; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v8, v0
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v4
|
|
; ZVFHMIN-NEXT: csrr a0, vlenb
|
|
; ZVFHMIN-NEXT: slli a0, a0, 3
|
|
; ZVFHMIN-NEXT: add a0, sp, a0
|
|
; ZVFHMIN-NEXT: addi a0, a0, 16
|
|
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vfmax.vv v8, v8, v16
|
|
; ZVFHMIN-NEXT: csrr a0, vlenb
|
|
; ZVFHMIN-NEXT: slli a0, a0, 3
|
|
; ZVFHMIN-NEXT: add a0, sp, a0
|
|
; ZVFHMIN-NEXT: addi a0, a0, 16
|
|
; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
|
|
; ZVFHMIN-NEXT: addi a0, sp, 16
|
|
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
|
|
; ZVFHMIN-NEXT: vmfeq.vv v7, v24, v24
|
|
; ZVFHMIN-NEXT: vmerge.vvm v16, v8, v24, v0
|
|
; ZVFHMIN-NEXT: vmv1r.v v0, v7
|
|
; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v8, v0
|
|
; ZVFHMIN-NEXT: vfmax.vv v16, v8, v16
|
|
; ZVFHMIN-NEXT: csrr a0, vlenb
|
|
; ZVFHMIN-NEXT: slli a0, a0, 3
|
|
; ZVFHMIN-NEXT: add a0, sp, a0
|
|
; ZVFHMIN-NEXT: addi a0, a0, 16
|
|
; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16
|
|
; ZVFHMIN-NEXT: csrr a0, vlenb
|
|
; ZVFHMIN-NEXT: slli a0, a0, 4
|
|
; ZVFHMIN-NEXT: add sp, sp, a0
|
|
; ZVFHMIN-NEXT: addi sp, sp, 16
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = call <vscale x 32 x half> @llvm.maximum.nxv32f16(<vscale x 32 x half> %a, <vscale x 32 x half> %b)
|
|
ret <vscale x 32 x half> %v
|
|
}
|
|
|
|
define <vscale x 1 x float> @vfmax_nxv1f32_vv(<vscale x 1 x float> %a, <vscale x 1 x float> %b) {
|
|
; CHECK-LABEL: vfmax_nxv1f32_vv:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vmfeq.vv v0, v8, v8
|
|
; CHECK-NEXT: vmerge.vvm v10, v8, v9, v0
|
|
; CHECK-NEXT: vmfeq.vv v0, v9, v9
|
|
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
|
|
; CHECK-NEXT: vfmax.vv v8, v8, v10
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 1 x float> @llvm.maximum.nxv1f32(<vscale x 1 x float> %a, <vscale x 1 x float> %b)
|
|
ret <vscale x 1 x float> %v
|
|
}
|
|
|
|
define <vscale x 2 x float> @vfmax_nxv2f32_vv(<vscale x 2 x float> %a, <vscale x 2 x float> %b) {
|
|
; CHECK-LABEL: vfmax_nxv2f32_vv:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
|
|
; CHECK-NEXT: vmfeq.vv v0, v8, v8
|
|
; CHECK-NEXT: vmerge.vvm v10, v8, v9, v0
|
|
; CHECK-NEXT: vmfeq.vv v0, v9, v9
|
|
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
|
|
; CHECK-NEXT: vfmax.vv v8, v8, v10
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 2 x float> @llvm.maximum.nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b)
|
|
ret <vscale x 2 x float> %v
|
|
}
|
|
|
|
define <vscale x 4 x float> @vfmax_nxv4f32_vv(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {
|
|
; CHECK-LABEL: vfmax_nxv4f32_vv:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
|
|
; CHECK-NEXT: vmfeq.vv v0, v8, v8
|
|
; CHECK-NEXT: vmerge.vvm v12, v8, v10, v0
|
|
; CHECK-NEXT: vmfeq.vv v0, v10, v10
|
|
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
|
|
; CHECK-NEXT: vfmax.vv v8, v8, v12
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 4 x float> @llvm.maximum.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b)
|
|
ret <vscale x 4 x float> %v
|
|
}
|
|
|
|
define <vscale x 8 x float> @vfmax_nxv8f32_vv(<vscale x 8 x float> %a, <vscale x 8 x float> %b) {
|
|
; CHECK-LABEL: vfmax_nxv8f32_vv:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
|
|
; CHECK-NEXT: vmfeq.vv v0, v8, v8
|
|
; CHECK-NEXT: vmerge.vvm v16, v8, v12, v0
|
|
; CHECK-NEXT: vmfeq.vv v0, v12, v12
|
|
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
|
|
; CHECK-NEXT: vfmax.vv v8, v8, v16
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 8 x float> @llvm.maximum.nxv8f32(<vscale x 8 x float> %a, <vscale x 8 x float> %b)
|
|
ret <vscale x 8 x float> %v
|
|
}
|
|
|
|
define <vscale x 16 x float> @vfmax_nxv16f32_vv(<vscale x 16 x float> %a, <vscale x 16 x float> %b) nounwind {
|
|
; CHECK-LABEL: vfmax_nxv16f32_vv:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
|
|
; CHECK-NEXT: vmfeq.vv v0, v8, v8
|
|
; CHECK-NEXT: vmfeq.vv v7, v16, v16
|
|
; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0
|
|
; CHECK-NEXT: vmv1r.v v0, v7
|
|
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
|
|
; CHECK-NEXT: vfmax.vv v8, v8, v24
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 16 x float> @llvm.maximum.nxv16f32(<vscale x 16 x float> %a, <vscale x 16 x float> %b)
|
|
ret <vscale x 16 x float> %v
|
|
}
|
|
|
|
define <vscale x 1 x double> @vfmax_nxv1f64_vv(<vscale x 1 x double> %a, <vscale x 1 x double> %b) {
|
|
; CHECK-LABEL: vfmax_nxv1f64_vv:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
|
|
; CHECK-NEXT: vmfeq.vv v0, v8, v8
|
|
; CHECK-NEXT: vmerge.vvm v10, v8, v9, v0
|
|
; CHECK-NEXT: vmfeq.vv v0, v9, v9
|
|
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
|
|
; CHECK-NEXT: vfmax.vv v8, v8, v10
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 1 x double> @llvm.maximum.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b)
|
|
ret <vscale x 1 x double> %v
|
|
}
|
|
|
|
define <vscale x 2 x double> @vfmax_nxv2f64_vv(<vscale x 2 x double> %a, <vscale x 2 x double> %b) {
|
|
; CHECK-LABEL: vfmax_nxv2f64_vv:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
|
|
; CHECK-NEXT: vmfeq.vv v0, v8, v8
|
|
; CHECK-NEXT: vmerge.vvm v12, v8, v10, v0
|
|
; CHECK-NEXT: vmfeq.vv v0, v10, v10
|
|
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
|
|
; CHECK-NEXT: vfmax.vv v8, v8, v12
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 2 x double> @llvm.maximum.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b)
|
|
ret <vscale x 2 x double> %v
|
|
}
|
|
|
|
define <vscale x 4 x double> @vfmax_nxv4f64_vv(<vscale x 4 x double> %a, <vscale x 4 x double> %b) {
|
|
; CHECK-LABEL: vfmax_nxv4f64_vv:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
|
|
; CHECK-NEXT: vmfeq.vv v0, v8, v8
|
|
; CHECK-NEXT: vmerge.vvm v16, v8, v12, v0
|
|
; CHECK-NEXT: vmfeq.vv v0, v12, v12
|
|
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
|
|
; CHECK-NEXT: vfmax.vv v8, v8, v16
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 4 x double> @llvm.maximum.nxv4f64(<vscale x 4 x double> %a, <vscale x 4 x double> %b)
|
|
ret <vscale x 4 x double> %v
|
|
}
|
|
|
|
define <vscale x 8 x double> @vfmax_nxv8f64_vv(<vscale x 8 x double> %a, <vscale x 8 x double> %b) nounwind {
|
|
; CHECK-LABEL: vfmax_nxv8f64_vv:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
|
|
; CHECK-NEXT: vmfeq.vv v0, v8, v8
|
|
; CHECK-NEXT: vmfeq.vv v7, v16, v16
|
|
; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0
|
|
; CHECK-NEXT: vmv1r.v v0, v7
|
|
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
|
|
; CHECK-NEXT: vfmax.vv v8, v8, v24
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 8 x double> @llvm.maximum.nxv8f64(<vscale x 8 x double> %a, <vscale x 8 x double> %b)
|
|
ret <vscale x 8 x double> %v
|
|
}
|
|
|
|
define <vscale x 1 x half> @vfmax_nxv1f16_vv_nnan(<vscale x 1 x half> %a, <vscale x 1 x half> %b) {
|
|
; ZVFH-LABEL: vfmax_nxv1f16_vv_nnan:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
|
|
; ZVFH-NEXT: vfmax.vv v8, v8, v9
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vfmax_nxv1f16_vv_nnan:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vfmax.vv v9, v9, v10
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
|
|
; ZVFHMIN-NEXT: ret
|
|
%v = call nnan <vscale x 1 x half> @llvm.maximum.nxv1f16(<vscale x 1 x half> %a, <vscale x 1 x half> %b)
|
|
ret <vscale x 1 x half> %v
|
|
}
|
|
|
|
define <vscale x 1 x half> @vfmax_nxv1f16_vv_nnana(<vscale x 1 x half> %a, <vscale x 1 x half> %b) {
|
|
; ZVFH-LABEL: vfmax_nxv1f16_vv_nnana:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
|
|
; ZVFH-NEXT: vmfeq.vv v0, v9, v9
|
|
; ZVFH-NEXT: vmv1r.v v10, v9
|
|
; ZVFH-NEXT: vfadd.vv v10, v8, v8, v0.t
|
|
; ZVFH-NEXT: vfmax.vv v8, v10, v9
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vfmax_nxv1f16_vv_nnana:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vfadd.vv v9, v10, v10
|
|
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
|
|
; ZVFHMIN-NEXT: vmv1r.v v9, v8
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10, v0.t
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vfmax.vv v9, v9, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
|
|
; ZVFHMIN-NEXT: ret
|
|
%c = fadd nnan <vscale x 1 x half> %a, %a
|
|
%v = call <vscale x 1 x half> @llvm.maximum.nxv1f16(<vscale x 1 x half> %c, <vscale x 1 x half> %b)
|
|
ret <vscale x 1 x half> %v
|
|
}
|
|
|
|
define <vscale x 1 x half> @vfmax_nxv1f16_vv_nnanb(<vscale x 1 x half> %a, <vscale x 1 x half> %b) {
|
|
; ZVFH-LABEL: vfmax_nxv1f16_vv_nnanb:
|
|
; ZVFH: # %bb.0:
|
|
; ZVFH-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
|
|
; ZVFH-NEXT: vmfeq.vv v0, v8, v8
|
|
; ZVFH-NEXT: vmv1r.v v10, v8
|
|
; ZVFH-NEXT: vfadd.vv v10, v9, v9, v0.t
|
|
; ZVFH-NEXT: vfmax.vv v8, v8, v10
|
|
; ZVFH-NEXT: ret
|
|
;
|
|
; ZVFHMIN-LABEL: vfmax_nxv1f16_vv_nnanb:
|
|
; ZVFHMIN: # %bb.0:
|
|
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vfadd.vv v8, v10, v10
|
|
; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
|
|
; ZVFHMIN-NEXT: vmv1r.v v8, v9
|
|
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10, v0.t
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; ZVFHMIN-NEXT: vfmax.vv v9, v9, v8
|
|
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
|
|
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
|
|
; ZVFHMIN-NEXT: ret
|
|
%c = fadd nnan <vscale x 1 x half> %b, %b
|
|
%v = call <vscale x 1 x half> @llvm.maximum.nxv1f16(<vscale x 1 x half> %a, <vscale x 1 x half> %c)
|
|
ret <vscale x 1 x half> %v
|
|
}
|