35e6bae62c
This reverts commit 61b2a0e3336aaa0132bbed06dc185aca4ff5d2db. Reason: AArch64TargetParserDef.inc not found while building clang
64 lines
2.6 KiB
C++
64 lines
2.6 KiB
C++
//===- ARMTargetDefEmitter.cpp - Generate data about ARM Architectures ----===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This tablegen backend exports information about CPUs, FPUs, architectures,
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// and features into a common format that can be used by both TargetParser and
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// the ARM and AArch64 backends.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/ADT/StringSet.h"
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#include "llvm/TableGen/Record.h"
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#include "llvm/TableGen/TableGenBackend.h"
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using namespace llvm;
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static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) {
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OS << "// Autogenerated by ARMTargetDefEmitter.cpp\n\n";
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// Look through all SubtargetFeature defs with the given FieldName, and
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// collect the set of all Values that that FieldName is set to.
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auto gatherSubtargetFeatureFieldValues = [&RK](StringRef FieldName) {
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llvm::StringSet<> Set;
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for (const Record *Rec : RK.getAllDerivedDefinitions("SubtargetFeature")) {
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if (Rec->getValueAsString("FieldName") == FieldName) {
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Set.insert(Rec->getValueAsString("Value"));
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}
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}
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return Set;
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};
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// The ARMProcFamilyEnum values are initialised by SubtargetFeature defs
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// which set the ARMProcFamily field. We can generate the enum from these defs
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// which look like this:
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//
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// def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
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// "Cortex-A5 ARM processors", []>;
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OS << "#ifndef ARM_PROCESSOR_FAMILY\n"
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<< "#define ARM_PROCESSOR_FAMILY(ENUM)\n"
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<< "#endif\n\n";
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const StringSet<> ARMProcFamilyVals =
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gatherSubtargetFeatureFieldValues("ARMProcFamily");
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for (const StringRef &Family : ARMProcFamilyVals.keys())
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OS << "ARM_PROCESSOR_FAMILY(" << Family << ")\n";
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OS << "\n#undef ARM_PROCESSOR_FAMILY\n\n";
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OS << "#ifndef ARM_ARCHITECTURE\n"
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<< "#define ARM_ARCHITECTURE(ENUM)\n"
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<< "#endif\n\n";
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// This should correspond to instances of the Architecture tablegen class.
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const StringSet<> ARMArchVals = gatherSubtargetFeatureFieldValues("ARMArch");
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for (const StringRef &Arch : ARMArchVals.keys())
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OS << "ARM_ARCHITECTURE(" << Arch << ")\n";
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OS << "\n#undef ARM_ARCHITECTURE\n\n";
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}
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static TableGen::Emitter::Opt
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X("gen-arm-target-def", EmitARMTargetDef,
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"Generate the ARM or AArch64 Architecture information header.");
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