4454152197
This strengthens the check to ensure the new mov's source class is compatible with the source register. This avoids using the register sized based checks in getMovOpcode, which don't quite understand AV superclasses correctly. As a side effect it also enables more folds into true16 movs. getMovOpcode should probably be deleted, or at least replaced with class check based logic. In this particular case other legality checks need to be mixed in with attempted IR changes, so I didn't try to push all of that into the opcode selection.
347 lines
13 KiB
LLVM
347 lines
13 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -enable-var-scope -check-prefixes=SI %s
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; RUN: llc -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=VI %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX11-TRUE16 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GFX11-FAKE16 %s
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define amdgpu_kernel void @br_cc_f16(
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; SI-LABEL: br_cc_f16:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
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; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_mov_b32 s6, -1
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; SI-NEXT: s_mov_b32 s10, s6
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_mov_b32 s4, s2
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; SI-NEXT: s_mov_b32 s5, s3
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; SI-NEXT: s_mov_b32 s11, s7
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; SI-NEXT: buffer_load_ushort v0, off, s[4:7], 0 glc
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 glc
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
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; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
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; SI-NEXT: v_cmp_nlt_f32_e32 vcc, v0, v1
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; SI-NEXT: s_cbranch_vccnz .LBB0_2
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; SI-NEXT: ; %bb.1: ; %one
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; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
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; SI-NEXT: s_branch .LBB0_3
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; SI-NEXT: .LBB0_2: ; %two
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; SI-NEXT: v_cvt_f16_f32_e32 v0, v1
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; SI-NEXT: .LBB0_3: ; %one
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; SI-NEXT: s_mov_b32 s2, s6
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; SI-NEXT: s_mov_b32 s3, s7
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; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: br_cc_f16:
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; VI: ; %bb.0: ; %entry
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; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; VI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x34
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; VI-NEXT: s_mov_b32 s7, 0xf000
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; VI-NEXT: s_mov_b32 s6, -1
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; VI-NEXT: s_mov_b32 s10, s6
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: s_mov_b32 s4, s2
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; VI-NEXT: s_mov_b32 s5, s3
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; VI-NEXT: s_mov_b32 s11, s7
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; VI-NEXT: buffer_load_ushort v0, off, s[4:7], 0 glc
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 glc
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: s_mov_b32 s2, s6
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; VI-NEXT: s_mov_b32 s3, s7
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; VI-NEXT: v_cmp_nlt_f16_e32 vcc, v0, v1
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; VI-NEXT: s_cbranch_vccnz .LBB0_2
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; VI-NEXT: ; %bb.1: ; %one
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; VI-NEXT: buffer_store_short v0, off, s[0:3], 0
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; VI-NEXT: s_endpgm
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; VI-NEXT: .LBB0_2: ; %two
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; VI-NEXT: buffer_store_short v1, off, s[0:3], 0
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; VI-NEXT: s_endpgm
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;
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; GFX11-TRUE16-LABEL: br_cc_f16:
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; GFX11-TRUE16: ; %bb.0: ; %entry
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; GFX11-TRUE16-NEXT: s_clause 0x1
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; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; GFX11-TRUE16-NEXT: s_load_b64 s[8:9], s[4:5], 0x34
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; GFX11-TRUE16-NEXT: s_mov_b32 s6, -1
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; GFX11-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
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; GFX11-TRUE16-NEXT: s_mov_b32 s10, s6
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; GFX11-TRUE16-NEXT: s_mov_b32 s11, s7
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; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-TRUE16-NEXT: s_mov_b32 s4, s2
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; GFX11-TRUE16-NEXT: s_mov_b32 s5, s3
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; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[4:7], 0 glc dlc
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; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
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; GFX11-TRUE16-NEXT: buffer_load_u16 v1, off, s[8:11], 0 glc dlc
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; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
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; GFX11-TRUE16-NEXT: s_mov_b32 s2, s6
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; GFX11-TRUE16-NEXT: s_mov_b32 s3, s7
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; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
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; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l
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; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v2.l, v2.h
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; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB0_2
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; GFX11-TRUE16-NEXT: ; %bb.1: ; %one
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; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0
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; GFX11-TRUE16-NEXT: s_endpgm
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; GFX11-TRUE16-NEXT: .LBB0_2: ; %two
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; GFX11-TRUE16-NEXT: buffer_store_b16 v1, off, s[0:3], 0
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; GFX11-TRUE16-NEXT: s_endpgm
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;
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; GFX11-FAKE16-LABEL: br_cc_f16:
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; GFX11-FAKE16: ; %bb.0: ; %entry
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; GFX11-FAKE16-NEXT: s_clause 0x1
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; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; GFX11-FAKE16-NEXT: s_load_b64 s[8:9], s[4:5], 0x34
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; GFX11-FAKE16-NEXT: s_mov_b32 s6, -1
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; GFX11-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
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; GFX11-FAKE16-NEXT: s_mov_b32 s10, s6
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; GFX11-FAKE16-NEXT: s_mov_b32 s11, s7
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; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-FAKE16-NEXT: s_mov_b32 s4, s2
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; GFX11-FAKE16-NEXT: s_mov_b32 s5, s3
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; GFX11-FAKE16-NEXT: buffer_load_u16 v0, off, s[4:7], 0 glc dlc
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; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
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; GFX11-FAKE16-NEXT: buffer_load_u16 v1, off, s[8:11], 0 glc dlc
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; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
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; GFX11-FAKE16-NEXT: s_mov_b32 s2, s6
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; GFX11-FAKE16-NEXT: s_mov_b32 s3, s7
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; GFX11-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0, v1
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; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB0_2
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; GFX11-FAKE16-NEXT: ; %bb.1: ; %one
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; GFX11-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0
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; GFX11-FAKE16-NEXT: s_endpgm
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; GFX11-FAKE16-NEXT: .LBB0_2: ; %two
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; GFX11-FAKE16-NEXT: buffer_store_b16 v1, off, s[0:3], 0
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; GFX11-FAKE16-NEXT: s_endpgm
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ptr addrspace(1) %r,
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ptr addrspace(1) %a,
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ptr addrspace(1) %b) {
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entry:
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%a.val = load volatile half, ptr addrspace(1) %a
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%b.val = load volatile half, ptr addrspace(1) %b
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%fcmp = fcmp olt half %a.val, %b.val
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br i1 %fcmp, label %one, label %two
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one:
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store half %a.val, ptr addrspace(1) %r
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ret void
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two:
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store half %b.val, ptr addrspace(1) %r
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ret void
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}
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define amdgpu_kernel void @br_cc_f16_imm_a(
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; SI-LABEL: br_cc_f16_imm_a:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_mov_b32 s6, -1
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_mov_b32 s4, s2
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; SI-NEXT: s_mov_b32 s5, s3
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; SI-NEXT: buffer_load_ushort v0, off, s[4:7], 0
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
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; SI-NEXT: v_cmp_nlt_f32_e32 vcc, 0.5, v0
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; SI-NEXT: s_cbranch_vccnz .LBB1_2
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; SI-NEXT: ; %bb.1: ; %one
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; SI-NEXT: s_mov_b32 s2, s6
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; SI-NEXT: s_mov_b32 s3, s7
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; SI-NEXT: v_mov_b32_e32 v0, 0x3800
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; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
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; SI-NEXT: s_endpgm
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; SI-NEXT: .LBB1_2: ; %two
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; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
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; SI-NEXT: s_mov_b32 s2, s6
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; SI-NEXT: s_mov_b32 s3, s7
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; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: br_cc_f16_imm_a:
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; VI: ; %bb.0: ; %entry
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; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; VI-NEXT: s_mov_b32 s7, 0xf000
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; VI-NEXT: s_mov_b32 s6, -1
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: s_mov_b32 s4, s2
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; VI-NEXT: s_mov_b32 s5, s3
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; VI-NEXT: buffer_load_ushort v0, off, s[4:7], 0
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; VI-NEXT: s_mov_b32 s2, s6
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; VI-NEXT: s_mov_b32 s3, s7
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: v_cmp_nlt_f16_e32 vcc, 0.5, v0
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; VI-NEXT: s_cbranch_vccnz .LBB1_2
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; VI-NEXT: ; %bb.1: ; %one
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; VI-NEXT: v_mov_b32_e32 v0, 0x3800
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; VI-NEXT: .LBB1_2: ; %two
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; VI-NEXT: buffer_store_short v0, off, s[0:3], 0
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; VI-NEXT: s_endpgm
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;
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; GFX11-TRUE16-LABEL: br_cc_f16_imm_a:
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; GFX11-TRUE16: ; %bb.0: ; %entry
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; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; GFX11-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
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; GFX11-TRUE16-NEXT: s_mov_b32 s6, -1
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; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-TRUE16-NEXT: s_mov_b32 s4, s2
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; GFX11-TRUE16-NEXT: s_mov_b32 s5, s3
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; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[4:7], 0
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; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
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; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l
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; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, 0.5, v1.l
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; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB1_2
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; GFX11-TRUE16-NEXT: ; %bb.1: ; %one
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; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x3800
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; GFX11-TRUE16-NEXT: .LBB1_2: ; %two
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; GFX11-TRUE16-NEXT: s_mov_b32 s2, s6
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; GFX11-TRUE16-NEXT: s_mov_b32 s3, s7
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; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0
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; GFX11-TRUE16-NEXT: s_endpgm
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;
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; GFX11-FAKE16-LABEL: br_cc_f16_imm_a:
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; GFX11-FAKE16: ; %bb.0: ; %entry
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; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; GFX11-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
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; GFX11-FAKE16-NEXT: s_mov_b32 s6, -1
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; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-FAKE16-NEXT: s_mov_b32 s4, s2
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; GFX11-FAKE16-NEXT: s_mov_b32 s5, s3
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; GFX11-FAKE16-NEXT: buffer_load_u16 v0, off, s[4:7], 0
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; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
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; GFX11-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, 0.5, v0
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; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB1_2
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; GFX11-FAKE16-NEXT: ; %bb.1: ; %one
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; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0x3800
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; GFX11-FAKE16-NEXT: .LBB1_2: ; %two
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; GFX11-FAKE16-NEXT: s_mov_b32 s2, s6
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; GFX11-FAKE16-NEXT: s_mov_b32 s3, s7
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; GFX11-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0
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; GFX11-FAKE16-NEXT: s_endpgm
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ptr addrspace(1) %r,
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ptr addrspace(1) %b) {
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entry:
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%b.val = load half, ptr addrspace(1) %b
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%fcmp = fcmp olt half 0xH3800, %b.val
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br i1 %fcmp, label %one, label %two
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one:
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store half 0xH3800, ptr addrspace(1) %r
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ret void
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two:
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store half %b.val, ptr addrspace(1) %r
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ret void
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}
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define amdgpu_kernel void @br_cc_f16_imm_b(
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; SI-LABEL: br_cc_f16_imm_b:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_mov_b32 s6, -1
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_mov_b32 s4, s2
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; SI-NEXT: s_mov_b32 s5, s3
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; SI-NEXT: buffer_load_ushort v0, off, s[4:7], 0
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
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; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0.5, v0
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; SI-NEXT: s_cbranch_vccnz .LBB2_2
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; SI-NEXT: ; %bb.1: ; %one
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; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
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; SI-NEXT: s_mov_b32 s2, s6
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; SI-NEXT: s_mov_b32 s3, s7
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; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
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; SI-NEXT: s_endpgm
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; SI-NEXT: .LBB2_2: ; %two
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; SI-NEXT: s_mov_b32 s2, s6
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; SI-NEXT: s_mov_b32 s3, s7
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; SI-NEXT: v_mov_b32_e32 v0, 0x3800
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; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: br_cc_f16_imm_b:
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; VI: ; %bb.0: ; %entry
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; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; VI-NEXT: s_mov_b32 s7, 0xf000
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; VI-NEXT: s_mov_b32 s6, -1
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: s_mov_b32 s4, s2
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; VI-NEXT: s_mov_b32 s5, s3
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; VI-NEXT: buffer_load_ushort v0, off, s[4:7], 0
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; VI-NEXT: s_mov_b32 s2, s6
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; VI-NEXT: s_mov_b32 s3, s7
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: v_cmp_ngt_f16_e32 vcc, 0.5, v0
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; VI-NEXT: s_cbranch_vccnz .LBB2_2
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; VI-NEXT: ; %bb.1: ; %one
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; VI-NEXT: buffer_store_short v0, off, s[0:3], 0
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; VI-NEXT: s_endpgm
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; VI-NEXT: .LBB2_2: ; %two
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; VI-NEXT: v_mov_b32_e32 v0, 0x3800
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; VI-NEXT: buffer_store_short v0, off, s[0:3], 0
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; VI-NEXT: s_endpgm
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;
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; GFX11-TRUE16-LABEL: br_cc_f16_imm_b:
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; GFX11-TRUE16: ; %bb.0: ; %entry
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; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; GFX11-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
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; GFX11-TRUE16-NEXT: s_mov_b32 s6, -1
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; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-TRUE16-NEXT: s_mov_b32 s4, s2
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; GFX11-TRUE16-NEXT: s_mov_b32 s5, s3
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; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[4:7], 0
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; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
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; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l
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; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, 0.5, v1.l
|
|
; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB2_2
|
|
; GFX11-TRUE16-NEXT: ; %bb.1: ; %two
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x3800
|
|
; GFX11-TRUE16-NEXT: .LBB2_2: ; %one
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s2, s6
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s3, s7
|
|
; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0
|
|
; GFX11-TRUE16-NEXT: s_endpgm
|
|
;
|
|
; GFX11-FAKE16-LABEL: br_cc_f16_imm_b:
|
|
; GFX11-FAKE16: ; %bb.0: ; %entry
|
|
; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s6, -1
|
|
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s4, s2
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s5, s3
|
|
; GFX11-FAKE16-NEXT: buffer_load_u16 v0, off, s[4:7], 0
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, 0.5, v0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB2_2
|
|
; GFX11-FAKE16-NEXT: ; %bb.1: ; %two
|
|
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0x3800
|
|
; GFX11-FAKE16-NEXT: .LBB2_2: ; %one
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s2, s6
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s3, s7
|
|
; GFX11-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0
|
|
; GFX11-FAKE16-NEXT: s_endpgm
|
|
ptr addrspace(1) %r,
|
|
ptr addrspace(1) %a) {
|
|
entry:
|
|
%a.val = load half, ptr addrspace(1) %a
|
|
%fcmp = fcmp olt half %a.val, 0xH3800
|
|
br i1 %fcmp, label %one, label %two
|
|
|
|
one:
|
|
store half %a.val, ptr addrspace(1) %r
|
|
ret void
|
|
|
|
two:
|
|
store half 0xH3800, ptr addrspace(1) %r
|
|
ret void
|
|
}
|