9e55d81c68
And rework the lit64() support to use it. The rules for when to add lit64() can be simplified and improved. In this change, however, we just follow the existing conventions on the assembler and disassembler sides. In codegen we do not (and normally should not need to) add explicit lit() and lit64() modifiers, so the codegen tests lose them. The change is an NFCI otherwise. Simplifies printing operands.
147 lines
5.2 KiB
LLVM
147 lines
5.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GCN,GFX12 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GCN,GFX1250 %s
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define amdgpu_ps <2 x float> @test_sub_u64_vv(i64 %a, i64 %b) {
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; GFX12-LABEL: test_sub_u64_vv:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v2
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; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX12-NEXT: v_sub_co_ci_u32_e64 v1, null, v1, v3, vcc_lo
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; GFX12-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: test_sub_u64_vv:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: v_sub_nc_u64_e32 v[0:1], v[0:1], v[2:3]
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; GFX1250-NEXT: ; return to shader part epilog
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%sub = sub i64 %a, %b
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%ret = bitcast i64 %sub to <2 x float>
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ret <2 x float> %ret
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}
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define amdgpu_ps <2 x float> @test_sub_u64_vs(i64 %a, i64 inreg %b) {
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; GFX12-LABEL: test_sub_u64_vs:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: v_sub_co_u32 v0, vcc_lo, v0, s0
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; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX12-NEXT: v_subrev_co_ci_u32_e64 v1, null, s1, v1, vcc_lo
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; GFX12-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: test_sub_u64_vs:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: v_sub_nc_u64_e64 v[0:1], v[0:1], s[0:1]
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; GFX1250-NEXT: ; return to shader part epilog
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%sub = sub i64 %a, %b
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%ret = bitcast i64 %sub to <2 x float>
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ret <2 x float> %ret
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}
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define amdgpu_ps <2 x float> @test_sub_u64_sv(i64 inreg %a, i64 %b) {
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; GFX12-LABEL: test_sub_u64_sv:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: v_sub_co_u32 v0, vcc_lo, s0, v0
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; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX12-NEXT: v_sub_co_ci_u32_e64 v1, null, s1, v1, vcc_lo
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; GFX12-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: test_sub_u64_sv:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: v_sub_nc_u64_e32 v[0:1], s[0:1], v[0:1]
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; GFX1250-NEXT: ; return to shader part epilog
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%sub = sub i64 %a, %b
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%ret = bitcast i64 %sub to <2 x float>
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ret <2 x float> %ret
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}
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define amdgpu_ps <2 x float> @test_sub_u64_ss(i64 inreg %a, i64 inreg %b) {
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; GCN-LABEL: test_sub_u64_ss:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_sub_nc_u64 s[0:1], s[0:1], s[2:3]
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; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GCN-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
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; GCN-NEXT: ; return to shader part epilog
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%sub = sub i64 %a, %b
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%ret = bitcast i64 %sub to <2 x float>
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ret <2 x float> %ret
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}
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define amdgpu_ps <2 x float> @test_sub_u64_inline_lit_v(i64 %a) {
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; GFX12-LABEL: test_sub_u64_inline_lit_v:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: v_sub_co_u32 v0, vcc_lo, 5, v0
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; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX12-NEXT: v_sub_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
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; GFX12-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: test_sub_u64_inline_lit_v:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: v_sub_nc_u64_e32 v[0:1], 5, v[0:1]
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; GFX1250-NEXT: ; return to shader part epilog
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%sub = sub i64 5, %a
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%ret = bitcast i64 %sub to <2 x float>
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ret <2 x float> %ret
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}
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define amdgpu_ps <2 x float> @test_sub_u64_v_inline_lit(i64 %a) {
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; GFX12-LABEL: test_sub_u64_v_inline_lit:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, -5
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; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
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; GFX12-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: test_sub_u64_v_inline_lit:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: v_add_nc_u64_e32 v[0:1], -5, v[0:1]
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; GFX1250-NEXT: ; return to shader part epilog
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%sub = sub i64 %a, 5
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%ret = bitcast i64 %sub to <2 x float>
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ret <2 x float> %ret
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}
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define amdgpu_ps <2 x float> @test_sub_u64_small_imm_v(i64 %a) {
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; GFX12-LABEL: test_sub_u64_small_imm_v:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: v_sub_co_u32 v0, vcc_lo, 0x1f4, v0
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; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX12-NEXT: v_sub_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
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; GFX12-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: test_sub_u64_small_imm_v:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: v_sub_nc_u64_e32 v[0:1], 0x1f4, v[0:1]
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; GFX1250-NEXT: ; return to shader part epilog
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%sub = sub i64 500, %a
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%ret = bitcast i64 %sub to <2 x float>
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ret <2 x float> %ret
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}
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define amdgpu_ps <2 x float> @test_sub_u64_64bit_imm_v(i64 %a) {
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; GFX12-LABEL: test_sub_u64_64bit_imm_v:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: v_sub_co_u32 v0, vcc_lo, 0x3b9ac9ff, v0
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; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX12-NEXT: v_sub_co_ci_u32_e64 v1, null, 1, v1, vcc_lo
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; GFX12-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: test_sub_u64_64bit_imm_v:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: v_sub_nc_u64_e32 v[0:1], 0x13b9ac9ff, v[0:1]
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; GFX1250-NEXT: ; return to shader part epilog
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%sub = sub i64 5294967295, %a
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%ret = bitcast i64 %sub to <2 x float>
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ret <2 x float> %ret
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}
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define amdgpu_ps <2 x float> @test_sub_u64_small_imm_s(i64 inreg %a) {
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; GCN-LABEL: test_sub_u64_small_imm_s:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_sub_nc_u64 s[0:1], 0x1f4, s[0:1]
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; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GCN-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
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; GCN-NEXT: ; return to shader part epilog
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%sub = sub i64 500, %a
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%ret = bitcast i64 %sub to <2 x float>
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ret <2 x float> %ret
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}
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