8122ccdca9
Hardware initializes a single value in ttmp9 which is either the workgroup ID X or cluster ID X. Most of this patch is a refactoring to use a single `PreloadedValue` enumerator for this value, instead of two enumerators `WORKGROUP_ID_X` and `CLUSTER_ID_X` referring to the same value. This makes it simpler to have a single attribute `amdgpu-no-workgroup-id-x` indicating that this value is not used, which in turns sets the TGID_EN_X bit appropriately to tell the hardware whether to initialize it. All of the above applies to Y and Z similarly. Fixes: LWPSCGFX13-568 Co-authored-by: Jay Foad <jay.foad@amd.com>
67 lines
3.3 KiB
LLVM
67 lines
3.3 KiB
LLVM
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -amdgpu-spill-sgpr-to-vgpr=0 -stop-after prologepilog -verify-machineinstrs %s -o - | FileCheck -check-prefix=AFTER-PEI %s
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; Test that the ScavengeFI is serialized in the SIMachineFunctionInfo.
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; AFTER-PEI-LABEL: {{^}}name: scavenge_fi
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; AFTER-PEI: machineFunctionInfo:
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; AFTER-PEI-NEXT: explicitKernArgSize: 12
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; AFTER-PEI-NEXT: maxKernArgAlign: 8
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; AFTER-PEI-NEXT: ldsSize: 0
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; AFTER-PEI-NEXT: gdsSize: 0
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; AFTER-PEI-NEXT: dynLDSAlign: 1
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; AFTER-PEI-NEXT: isEntryFunction: true
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; AFTER-PEI-NEXT: isChainFunction: false
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; AFTER-PEI-NEXT: noSignedZerosFPMath: false
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; AFTER-PEI-NEXT: memoryBound: false
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; AFTER-PEI-NEXT: waveLimiter: false
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; AFTER-PEI-NEXT: hasSpilledSGPRs: true
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; AFTER-PEI-NEXT: hasSpilledVGPRs: false
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; AFTER-PEI-NEXT: numWaveDispatchSGPRs: 0
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; AFTER-PEI-NEXT: numWaveDispatchVGPRs: 0
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; AFTER-PEI-NEXT: scratchRSrcReg: '$sgpr68_sgpr69_sgpr70_sgpr71'
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; AFTER-PEI-NEXT: frameOffsetReg: '$fp_reg'
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; AFTER-PEI-NEXT: stackPtrOffsetReg: '$sgpr32'
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; AFTER-PEI-NEXT: bytesInStackArgArea: 0
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; AFTER-PEI-NEXT: returnsVoid: true
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; AFTER-PEI-NEXT: argumentInfo:
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; AFTER-PEI-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
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; AFTER-PEI-NEXT: kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }
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; AFTER-PEI-NEXT: workGroupIDX: { reg: '$sgpr6' }
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; AFTER-PEI-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr7' }
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; AFTER-PEI-NEXT: workItemIDX: { reg: '$vgpr0' }
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; AFTER-PEI-NEXT: psInputAddr: 0
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; AFTER-PEI-NEXT: psInputEnable: 0
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; AFTER-PEI-NEXT: maxMemoryClusterDWords: 8
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; AFTER-PEI-NEXT: mode:
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; AFTER-PEI-NEXT: ieee: true
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; AFTER-PEI-NEXT: dx10-clamp: true
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; AFTER-PEI-NEXT: fp32-input-denormals: true
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; AFTER-PEI-NEXT: fp32-output-denormals: true
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; AFTER-PEI-NEXT: fp64-fp16-input-denormals: true
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; AFTER-PEI-NEXT: fp64-fp16-output-denormals: true
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; AFTER-PEI-NEXT: highBitsOf32BitAddress: 0
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; AFTER-PEI-NEXT: occupancy: 5
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; AFTER-PEI-NEXT: scavengeFI: '%stack.3'
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; AFTER-PEI-NEXT: vgprForAGPRCopy: ''
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; AFTER-PEI-NEXT: sgprForEXECCopy: ''
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; AFTER-PEI-NEXT: longBranchReservedReg: ''
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; AFTER-PEI-NEXT: hasInitWholeWave: false
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; AFTER-PEI-NEXT: dynamicVGPRBlockSize: 0
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; AFTER-PEI-NEXT: scratchReservedForDynamicVGPRs: 0
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; AFTER-PEI-NEXT: isWholeWaveFunction: false
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; AFTER-PEI-NEXT: body:
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define amdgpu_kernel void @scavenge_fi(ptr addrspace(1) %out, i32 %in) #0 {
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%wide.sgpr0 = call <32 x i32> asm sideeffect "; def $0", "=s" () #0
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%wide.sgpr1 = call <32 x i32> asm sideeffect "; def $0", "=s" () #0
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%wide.sgpr2 = call <32 x i32> asm sideeffect "; def $0", "=s" () #0
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%wide.sgpr3 = call <32 x i32> asm sideeffect "; def $0", "=s" () #0
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call void asm sideeffect "; use $0", "s"(<32 x i32> %wide.sgpr0) #0
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call void asm sideeffect "; use $0", "s"(<32 x i32> %wide.sgpr1) #0
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call void asm sideeffect "; use $0", "s"(<32 x i32> %wide.sgpr2) #0
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call void asm sideeffect "; use $0", "s"(<32 x i32> %wide.sgpr3) #0
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ret void
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}
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attributes #0 = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-cluster-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-cluster-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-cluster-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" }
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