8149cbfecd
Fixes #124932. This patch implements the getIPRACSRegs hook for RISC-V, similar to its introduction for x86 in commit 14b567d. This hook is necessary for correct code generation when Interprocedural Register Allocation (IPRA) is enabled, ensuring that the return address register (ra / x1) is correctly saved and restored when needed. Unlike the x86 implementation, this patch only saves ra and does not yet include the frame pointer (fp). Further investigation is required to determine whether fp should also be preserved in all cases. The test case is representative of a miscompile observed in the GCC torture suite (20090113-3.c), though similar failures occur in SPEC’s xz benchmark.
70 lines
2.7 KiB
TableGen
70 lines
2.7 KiB
TableGen
//===-- RISCVCallingConv.td - Calling Conventions RISC-V ---*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This describes the calling conventions for the RISC-V architecture.
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//
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//===----------------------------------------------------------------------===//
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// The RISC-V calling convention is handled with custom code in
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// RISCVISelLowering.cpp (CC_RISCV).
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def CSR_ILP32E_LP64E : CalleeSavedRegs<(add X1, X8, X9)>;
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def CSR_ILP32_LP64
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: CalleeSavedRegs<(add CSR_ILP32E_LP64E, (sequence "X%u", 18, 27))>;
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def CSR_ILP32F_LP64F
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: CalleeSavedRegs<(add CSR_ILP32_LP64,
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F8_F, F9_F, (sequence "F%u_F", 18, 27))>;
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def CSR_ILP32D_LP64D
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: CalleeSavedRegs<(add CSR_ILP32_LP64,
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F8_D, F9_D, (sequence "F%u_D", 18, 27))>;
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defvar CSR_V = (add (sequence "V%u", 1, 7), (sequence "V%u", 24, 31),
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V2M2, V4M2, V6M2, V24M2, V26M2, V28M2, V30M2,
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V4M4, V24M4, V28M4, V24M8);
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def CSR_ILP32_LP64_V
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: CalleeSavedRegs<(add CSR_ILP32_LP64, CSR_V)>;
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def CSR_ILP32F_LP64F_V
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: CalleeSavedRegs<(add CSR_ILP32F_LP64F, CSR_V)>;
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def CSR_ILP32D_LP64D_V
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: CalleeSavedRegs<(add CSR_ILP32D_LP64D, CSR_V)>;
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// Needed for implementation of RISCVRegisterInfo::getNoPreservedMask()
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def CSR_NoRegs : CalleeSavedRegs<(add)>;
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def CSR_IPRA : CalleeSavedRegs<(add X1)>;
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// Interrupt handler needs to save/restore all registers that are used,
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// both Caller and Callee saved registers.
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def CSR_Interrupt : CalleeSavedRegs<(add X1, (sequence "X%u", 5, 31))>;
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// Same as CSR_Interrupt, but including all 32-bit FP registers.
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def CSR_XLEN_F32_Interrupt: CalleeSavedRegs<(add CSR_Interrupt,
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(sequence "F%u_F", 0, 31))>;
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// Same as CSR_Interrupt, but including all 64-bit FP registers.
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def CSR_XLEN_F64_Interrupt: CalleeSavedRegs<(add CSR_Interrupt,
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(sequence "F%u_D", 0, 31))>;
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// Same as CSR_Interrupt, but excluding X16-X31.
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def CSR_Interrupt_RVE : CalleeSavedRegs<(sub CSR_Interrupt,
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(sequence "X%u", 16, 31))>;
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// Same as CSR_XLEN_F32_Interrupt, but excluding X16-X31.
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def CSR_XLEN_F32_Interrupt_RVE: CalleeSavedRegs<(sub CSR_XLEN_F32_Interrupt,
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(sequence "X%u", 16, 31))>;
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// Same as CSR_XLEN_F64_Interrupt, but excluding X16-X31.
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def CSR_XLEN_F64_Interrupt_RVE: CalleeSavedRegs<(sub CSR_XLEN_F64_Interrupt,
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(sequence "X%u", 16, 31))>;
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