859c871184
This change introduces a default schedule model for the RISCV target which leaves everything unchanged except the MicroOpBufferSize. The default value of this flag in NoSched is 0. Both configurations represent in order cores (i.e. no reorder window), the difference between them comes down to whether heuristics other than latency are allowed to apply. (Implementation details below) I left the processor models which explicitly set MicroOpBufferSize=0 unchanged in this patch, but strongly suspect we should change those too. Honestly, I think the LLVM wide default for this flag should be changed, but don't have the energy to manage the updates for all targets. Implementation wise, the effect of this change is that schedule units which are ready to run *except that* one of their predecessors may not have completed yet are added to the Available list, not the Pending one. The result of this is that it becomes possible to chose to schedule a node before it's ready cycle if the heuristics prefer. This is essentially chosing to insert a resource stall instead of e.g. increasing register pressure. Note that I was initially concerned there might be a correctness aspect (as in some kind of exposed pipeline design), but the generic scheduler doesn't seem to know how to insert noop instructions. Without that, a program wouldn't be guaranteed to schedule on an exposed pipeline depending on the program and schedule model in question. The effect of this is that we sometimes prefer register pressure in codegen results. This is mostly churn (or small wins) on scalar because we have many more registers, but is of major importance on vector - particularly high LMUL - because we effectively have many fewer registers and the relative cost of spilling is much higher. This is a significant improvement on high LMUL code quality for default rva23u configurations - or any non -mcpu vector configuration for that matter. Fixes #107532
607 lines
31 KiB
TableGen
607 lines
31 KiB
TableGen
//===-- RISCVProcessors.td - RISC-V Processors -------------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// RISC-V processors supported.
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//===----------------------------------------------------------------------===//
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// Predefined scheduling direction.
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defvar TopDown = [{ MISched::TopDown }];
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defvar BottomUp = [{ MISched::BottomUp }];
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defvar Bidirectional = [{ MISched::Bidirectional }];
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class RISCVTuneInfo {
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bits<8> PrefFunctionAlignment = 1;
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bits<8> PrefLoopAlignment = 1;
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// Information needed by LoopDataPrefetch.
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bits<16> CacheLineSize = 0;
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bits<16> PrefetchDistance = 0;
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bits<16> MinPrefetchStride = 1;
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bits<32> MaxPrefetchIterationsAhead = -1;
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bits<32> MinimumJumpTableEntries = 5;
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// Tail duplication threshold at -O3.
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bits<32> TailDupAggressiveThreshold = 6;
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bits<32> MaxStoresPerMemsetOptSize = 4;
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bits<32> MaxStoresPerMemset = 8;
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bits<32> MaxGluedStoresPerMemcpy = 0;
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bits<32> MaxStoresPerMemcpyOptSize = 4;
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bits<32> MaxStoresPerMemcpy = 8;
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bits<32> MaxStoresPerMemmoveOptSize = 4;
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bits<32> MaxStoresPerMemmove = 8;
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bits<32> MaxLoadsPerMemcmpOptSize = 4;
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bits<32> MaxLoadsPerMemcmp = 8;
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// The direction of PostRA scheduling.
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code PostRASchedDirection = TopDown;
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}
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def RISCVTuneInfoTable : GenericTable {
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let FilterClass = "RISCVTuneInfo";
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let CppTypeName = "RISCVTuneInfo";
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let Fields = ["Name", "PrefFunctionAlignment", "PrefLoopAlignment",
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"CacheLineSize", "PrefetchDistance", "MinPrefetchStride",
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"MaxPrefetchIterationsAhead", "MinimumJumpTableEntries",
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"TailDupAggressiveThreshold", "MaxStoresPerMemsetOptSize",
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"MaxStoresPerMemset", "MaxGluedStoresPerMemcpy",
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"MaxStoresPerMemcpyOptSize", "MaxStoresPerMemcpy",
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"MaxStoresPerMemmoveOptSize", "MaxStoresPerMemmove",
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"MaxLoadsPerMemcmpOptSize", "MaxLoadsPerMemcmp",
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"PostRASchedDirection"];
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}
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def getRISCVTuneInfo : SearchIndex {
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let Table = RISCVTuneInfoTable;
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let Key = ["Name"];
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}
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class GenericTuneInfo: RISCVTuneInfo;
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class RISCVProcessorModel<string n,
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SchedMachineModel m,
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list<SubtargetFeature> f,
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list<SubtargetFeature> tunef = [],
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string default_march = "">
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: ProcessorModel<n, m, f, tunef> {
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string DefaultMarch = default_march;
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int MVendorID = 0;
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int MArchID = 0;
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int MImpID = 0;
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}
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class RISCVTuneProcessorModel<string n,
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SchedMachineModel m,
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list<SubtargetFeature> tunef = [],
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list<SubtargetFeature> f = []>
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: ProcessorModel<n, m, f,tunef>;
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defvar GenericTuneFeatures = [TuneOptimizedNF2SegmentLoadStore];
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// Adjust the default cost model to enable all heuristics, not just latency
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// In particular, this enables register pressure heustics which are very
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// important for high LMUL vector code, and have little negative impact
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// on other configurations,
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def GenericModel : SchedMachineModel {
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let MicroOpBufferSize = 1;
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let CompleteModel = 0;
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}
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def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32",
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GenericModel,
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[Feature32Bit,
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FeatureStdExtI],
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GenericTuneFeatures>,
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GenericTuneInfo;
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def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64",
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GenericModel,
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[Feature64Bit,
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FeatureStdExtI],
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GenericTuneFeatures>,
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GenericTuneInfo;
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// Support generic for compatibility with other targets. The triple will be used
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// to change to the appropriate rv32/rv64 version.
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def GENERIC : RISCVTuneProcessorModel<"generic", GenericModel>, GenericTuneInfo;
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def MIPS_P8700 : RISCVProcessorModel<"mips-p8700",
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MIPSP8700Model,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC,
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FeatureStdExtZba,
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FeatureStdExtZbb,
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FeatureStdExtZifencei,
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FeatureStdExtZicsr,
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FeatureVendorXMIPSCMove,
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FeatureVendorXMIPSLSP],
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[TuneMIPSP8700]>;
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def ROCKET_RV32 : RISCVProcessorModel<"rocket-rv32",
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RocketModel,
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[Feature32Bit,
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FeatureStdExtI,
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FeatureStdExtZifencei,
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FeatureStdExtZicsr]>;
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def ROCKET_RV64 : RISCVProcessorModel<"rocket-rv64",
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RocketModel,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZifencei,
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FeatureStdExtZicsr]>;
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def ROCKET : RISCVTuneProcessorModel<"rocket",
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RocketModel>;
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defvar SiFive7TuneFeatures = [TuneSiFive7, TuneNoDefaultUnroll,
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TuneShortForwardBranchOpt,
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TunePostRAScheduler];
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def SIFIVE_7 : RISCVTuneProcessorModel<"sifive-7-series",
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SiFive7Model, SiFive7TuneFeatures>;
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def SIFIVE_E20 : RISCVProcessorModel<"sifive-e20",
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RocketModel,
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[Feature32Bit,
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FeatureStdExtI,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtC]>;
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def SIFIVE_E21 : RISCVProcessorModel<"sifive-e21",
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RocketModel,
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[Feature32Bit,
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FeatureStdExtI,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtC]>;
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def SIFIVE_E24 : RISCVProcessorModel<"sifive-e24",
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RocketModel,
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[Feature32Bit,
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FeatureStdExtI,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtC]>;
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def SIFIVE_E31 : RISCVProcessorModel<"sifive-e31",
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RocketModel,
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[Feature32Bit,
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FeatureStdExtI,
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FeatureStdExtZifencei,
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FeatureStdExtZicsr,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtC]>;
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def SIFIVE_E34 : RISCVProcessorModel<"sifive-e34",
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RocketModel,
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[Feature32Bit,
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FeatureStdExtI,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtC]>;
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def SIFIVE_E76 : RISCVProcessorModel<"sifive-e76",
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SiFive7Model,
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[Feature32Bit,
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FeatureStdExtI,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtC],
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SiFive7TuneFeatures>;
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def SIFIVE_S21 : RISCVProcessorModel<"sifive-s21",
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RocketModel,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtC]>;
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def SIFIVE_S51 : RISCVProcessorModel<"sifive-s51",
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RocketModel,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtC]>;
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def SIFIVE_S54 : RISCVProcessorModel<"sifive-s54",
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RocketModel,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC]>;
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def SIFIVE_S76 : RISCVProcessorModel<"sifive-s76",
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SiFive7Model,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC,
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FeatureStdExtZihintpause],
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SiFive7TuneFeatures>;
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def SIFIVE_U54 : RISCVProcessorModel<"sifive-u54",
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RocketModel,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC]>;
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def SIFIVE_U74 : RISCVProcessorModel<"sifive-u74",
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SiFive7Model,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC],
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SiFive7TuneFeatures>;
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defvar SiFiveX280TuneFeatures = !listconcat(SiFive7TuneFeatures,
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[TuneDLenFactor2,
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TuneOptimizedZeroStrideLoad,
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TuneOptimizedNF2SegmentLoadStore]);
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def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC,
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FeatureStdExtV,
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FeatureStdExtZvl512b,
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FeatureStdExtZfh,
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FeatureStdExtZvfh,
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FeatureStdExtZba,
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FeatureStdExtZbb],
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SiFiveX280TuneFeatures>;
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defvar SiFiveP400TuneFeatures = [TuneNoDefaultUnroll,
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TuneConditionalCompressedMoveFusion,
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TuneLUIADDIFusion,
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TuneAUIPCADDIFusion,
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TunePostRAScheduler];
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def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model,
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!listconcat(RVA22U64Features,
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[FeatureStdExtZifencei,
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FeatureStdExtZihintntl,
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FeatureUnalignedScalarMem,
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FeatureUnalignedVectorMem]),
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SiFiveP400TuneFeatures>;
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def SIFIVE_P470 : RISCVProcessorModel<"sifive-p470", SiFiveP400Model,
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!listconcat(RVA22U64Features,
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[FeatureStdExtV,
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FeatureStdExtZifencei,
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FeatureStdExtZihintntl,
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FeatureStdExtZvl128b,
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FeatureStdExtZvbb,
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FeatureStdExtZvknc,
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FeatureStdExtZvkng,
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FeatureStdExtZvksc,
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FeatureStdExtZvksg,
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FeatureVendorXSiFivecdiscarddlone,
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FeatureVendorXSiFivecflushdlone,
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FeatureUnalignedScalarMem,
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FeatureUnalignedVectorMem]),
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!listconcat(SiFiveP400TuneFeatures,
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[TuneNoSinkSplatOperands,
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TuneVXRMPipelineFlush])>;
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defvar SiFiveP500TuneFeatures = [TuneNoDefaultUnroll,
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TuneConditionalCompressedMoveFusion,
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TuneLUIADDIFusion,
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TuneAUIPCADDIFusion,
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TunePostRAScheduler];
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def SIFIVE_P550 : RISCVProcessorModel<"sifive-p550", SiFiveP500Model,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC,
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FeatureStdExtZba,
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FeatureStdExtZbb],
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SiFiveP500TuneFeatures>;
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def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model,
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!listconcat(RVA22U64Features,
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[FeatureStdExtV,
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FeatureStdExtZifencei,
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FeatureStdExtZihintntl,
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FeatureStdExtZvl128b,
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FeatureStdExtZvbb,
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FeatureStdExtZvknc,
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FeatureStdExtZvkng,
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FeatureStdExtZvksc,
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FeatureStdExtZvksg,
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FeatureUnalignedScalarMem,
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FeatureUnalignedVectorMem]),
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[TuneNoDefaultUnroll,
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TuneConditionalCompressedMoveFusion,
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TuneLUIADDIFusion,
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TuneAUIPCADDIFusion,
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TuneNoSinkSplatOperands,
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TuneVXRMPipelineFlush,
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TunePostRAScheduler]>;
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def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",
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SyntacoreSCR1Model,
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[Feature32Bit,
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FeatureStdExtI,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtC],
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[TuneNoDefaultUnroll]>;
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def SYNTACORE_SCR1_MAX : RISCVProcessorModel<"syntacore-scr1-max",
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SyntacoreSCR1Model,
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[Feature32Bit,
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FeatureStdExtI,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtC],
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[TuneNoDefaultUnroll]>;
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def SYNTACORE_SCR3_RV32 : RISCVProcessorModel<"syntacore-scr3-rv32",
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SyntacoreSCR3RV32Model,
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[Feature32Bit,
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FeatureStdExtI,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtC],
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[TuneNoDefaultUnroll, TunePostRAScheduler]>;
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def SYNTACORE_SCR3_RV64 : RISCVProcessorModel<"syntacore-scr3-rv64",
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SyntacoreSCR3RV64Model,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtC],
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[TuneNoDefaultUnroll, TunePostRAScheduler]>;
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def SYNTACORE_SCR4_RV32 : RISCVProcessorModel<"syntacore-scr4-rv32",
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SyntacoreSCR4RV32Model,
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[Feature32Bit,
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FeatureStdExtI,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC],
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[TuneNoDefaultUnroll, TunePostRAScheduler]>;
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def SYNTACORE_SCR4_RV64 : RISCVProcessorModel<"syntacore-scr4-rv64",
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SyntacoreSCR4RV64Model,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC],
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[TuneNoDefaultUnroll, TunePostRAScheduler]>;
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def SYNTACORE_SCR5_RV32 : RISCVProcessorModel<"syntacore-scr5-rv32",
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SyntacoreSCR5RV32Model,
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[Feature32Bit,
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FeatureStdExtI,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC],
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[TuneNoDefaultUnroll, TunePostRAScheduler]>;
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def SYNTACORE_SCR5_RV64 : RISCVProcessorModel<"syntacore-scr5-rv64",
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SyntacoreSCR5RV64Model,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC],
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[TuneNoDefaultUnroll, TunePostRAScheduler]>;
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def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
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SyntacoreSCR7Model,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC,
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FeatureStdExtV,
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FeatureStdExtZba,
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FeatureStdExtZbb,
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FeatureStdExtZbc,
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FeatureStdExtZbs,
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FeatureStdExtZkn],
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[TuneNoDefaultUnroll, TunePostRAScheduler]>;
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def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8",
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TTAscalonD8Model,
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!listconcat(RVA23S64Features,
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[FeatureStdExtSmaia,
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FeatureStdExtSsaia,
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FeatureStdExtSscofpmf,
|
|
FeatureStdExtSsstrict,
|
|
FeatureStdExtZfbfmin,
|
|
FeatureStdExtZfh,
|
|
FeatureStdExtZicsr,
|
|
FeatureStdExtZvbc,
|
|
FeatureStdExtZvfbfmin,
|
|
FeatureStdExtZvfbfwma,
|
|
FeatureStdExtZvfh,
|
|
FeatureStdExtZvkng,
|
|
FeatureStdExtZvl256b,
|
|
FeatureUnalignedScalarMem,
|
|
FeatureUnalignedVectorMem]),
|
|
[TuneNoDefaultUnroll,
|
|
TuneOptimizedZeroStrideLoad,
|
|
TunePostRAScheduler]>;
|
|
|
|
def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
|
|
GenericModel,
|
|
[Feature64Bit,
|
|
FeatureStdExtI,
|
|
FeatureStdExtZifencei,
|
|
FeatureStdExtZicsr,
|
|
FeatureStdExtZicntr,
|
|
FeatureStdExtZihpm,
|
|
FeatureStdExtZihintpause,
|
|
FeatureStdExtM,
|
|
FeatureStdExtA,
|
|
FeatureStdExtF,
|
|
FeatureStdExtD,
|
|
FeatureStdExtC,
|
|
FeatureStdExtZba,
|
|
FeatureStdExtZbb,
|
|
FeatureStdExtZbc,
|
|
FeatureStdExtZbs,
|
|
FeatureStdExtZicbom,
|
|
FeatureStdExtZicbop,
|
|
FeatureStdExtZicboz,
|
|
FeatureVendorXVentanaCondOps],
|
|
[TuneVentanaVeyron,
|
|
TuneLUIADDIFusion,
|
|
TuneAUIPCADDIFusion,
|
|
TuneZExtHFusion,
|
|
TuneZExtWFusion,
|
|
TuneShiftedZExtWFusion,
|
|
TuneLDADDFusion]> {
|
|
let MVendorID = 0x61f;
|
|
let MArchID = 0x8000000000010000;
|
|
let MImpID = 0x111;
|
|
}
|
|
|
|
def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
|
|
XiangShanNanHuModel,
|
|
[Feature64Bit,
|
|
FeatureStdExtI,
|
|
FeatureStdExtZicsr,
|
|
FeatureStdExtZifencei,
|
|
FeatureStdExtM,
|
|
FeatureStdExtA,
|
|
FeatureStdExtF,
|
|
FeatureStdExtD,
|
|
FeatureStdExtC,
|
|
FeatureStdExtZba,
|
|
FeatureStdExtZbb,
|
|
FeatureStdExtZbc,
|
|
FeatureStdExtZbs,
|
|
FeatureStdExtZkn,
|
|
FeatureStdExtZksed,
|
|
FeatureStdExtZksh,
|
|
FeatureStdExtSvinval,
|
|
FeatureStdExtZicbom,
|
|
FeatureStdExtZicboz],
|
|
[TuneNoDefaultUnroll,
|
|
TuneZExtHFusion,
|
|
TuneZExtWFusion,
|
|
TuneShiftedZExtWFusion]>;
|
|
|
|
def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
|
|
GenericModel,
|
|
!listconcat(RVA22S64Features,
|
|
[FeatureStdExtV,
|
|
FeatureStdExtSscofpmf,
|
|
FeatureStdExtSstc,
|
|
FeatureStdExtSvnapot,
|
|
FeatureStdExtZbc,
|
|
FeatureStdExtZbkc,
|
|
FeatureStdExtZfh,
|
|
FeatureStdExtZicond,
|
|
FeatureStdExtZvfh,
|
|
FeatureStdExtZvkt,
|
|
FeatureStdExtZvl256b,
|
|
FeatureUnalignedScalarMem]),
|
|
[TuneDLenFactor2,
|
|
TuneOptimizedNF2SegmentLoadStore,
|
|
TuneOptimizedNF3SegmentLoadStore,
|
|
TuneOptimizedNF4SegmentLoadStore,
|
|
TuneVXRMPipelineFlush]> {
|
|
let MVendorID = 0x710;
|
|
let MArchID = 0x8000000058000001;
|
|
let MImpID = 0x1000000049772200;
|
|
}
|
|
|
|
def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3",
|
|
GenericModel,
|
|
[Feature32Bit,
|
|
FeatureStdExtI,
|
|
FeatureStdExtM,
|
|
FeatureStdExtA,
|
|
FeatureStdExtC,
|
|
FeatureStdExtZicsr,
|
|
FeatureStdExtZifencei,
|
|
FeatureStdExtZba,
|
|
FeatureStdExtZbb,
|
|
FeatureStdExtZbs,
|
|
FeatureStdExtZbkb,
|
|
FeatureStdExtZcb,
|
|
FeatureStdExtZcmp]>;
|