83783e8bec
Found using https://github.com/codespell-project/codespell ``` codespell RISCV --write-changes \ --ignore-words-list=FPR,fpr,VAs,ORE,WorstCase,hart,sie,MIs,FLE,fle,CarryIn,vor,OLT,VILL,vill,bu,pass-thru ```
138 lines
4.5 KiB
C++
138 lines
4.5 KiB
C++
//===- RISCVVectorMaskDAGMutation.cpp - RISC-V Vector Mask DAGMutation ----===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// A schedule mutation that adds an artificial dependency between masks producer
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// instructions and masked instructions, so that we can reduce the live range
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// overlaps of mask registers.
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//
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// The reason why we need to do this:
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// 1. When tracking register pressure, we don't track physical registers.
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// 2. We have a RegisterClass for mask register (which is `VMV0`), but we don't
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// use it in most RVV pseudos (only used in inline asm constraint and add/sub
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// with carry instructions). Instead, we use physical register V0 directly
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// and insert a `$v0 = COPY ...` before the use. And, there is a fundamental
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// issue in register allocator when handling RegisterClass with only one
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// physical register, so we can't simply replace V0 with VMV0.
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// 3. For mask producers, we are using VR RegisterClass (we can allocate V0-V31
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// to it). So if V0 is not available, there are still 31 available registers
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// out there.
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//
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// This means that the RegPressureTracker can't track the pressure of mask
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// registers correctly.
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//
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// This schedule mutation is a workaround to fix this issue.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/RISCVBaseInfo.h"
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "RISCVRegisterInfo.h"
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#include "RISCVTargetMachine.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/ScheduleDAGInstrs.h"
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#include "llvm/CodeGen/ScheduleDAGMutation.h"
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#include "llvm/TargetParser/RISCVTargetParser.h"
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#define DEBUG_TYPE "machine-scheduler"
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namespace llvm {
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static inline bool isVectorMaskProducer(const MachineInstr *MI) {
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switch (RISCV::getRVVMCOpcode(MI->getOpcode())) {
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// Vector Mask Instructions
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case RISCV::VMAND_MM:
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case RISCV::VMNAND_MM:
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case RISCV::VMANDN_MM:
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case RISCV::VMXOR_MM:
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case RISCV::VMOR_MM:
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case RISCV::VMNOR_MM:
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case RISCV::VMORN_MM:
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case RISCV::VMXNOR_MM:
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case RISCV::VMSBF_M:
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case RISCV::VMSIF_M:
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case RISCV::VMSOF_M:
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// Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
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case RISCV::VMADC_VV:
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case RISCV::VMADC_VX:
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case RISCV::VMADC_VI:
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case RISCV::VMADC_VVM:
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case RISCV::VMADC_VXM:
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case RISCV::VMADC_VIM:
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case RISCV::VMSBC_VV:
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case RISCV::VMSBC_VX:
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case RISCV::VMSBC_VVM:
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case RISCV::VMSBC_VXM:
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// Vector Integer Compare Instructions
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case RISCV::VMSEQ_VV:
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case RISCV::VMSEQ_VX:
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case RISCV::VMSEQ_VI:
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case RISCV::VMSNE_VV:
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case RISCV::VMSNE_VX:
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case RISCV::VMSNE_VI:
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case RISCV::VMSLT_VV:
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case RISCV::VMSLT_VX:
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case RISCV::VMSLTU_VV:
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case RISCV::VMSLTU_VX:
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case RISCV::VMSLE_VV:
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case RISCV::VMSLE_VX:
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case RISCV::VMSLE_VI:
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case RISCV::VMSLEU_VV:
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case RISCV::VMSLEU_VX:
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case RISCV::VMSLEU_VI:
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case RISCV::VMSGTU_VX:
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case RISCV::VMSGTU_VI:
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case RISCV::VMSGT_VX:
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case RISCV::VMSGT_VI:
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// Vector Floating-Point Compare Instructions
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case RISCV::VMFEQ_VV:
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case RISCV::VMFEQ_VF:
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case RISCV::VMFNE_VV:
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case RISCV::VMFNE_VF:
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case RISCV::VMFLT_VV:
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case RISCV::VMFLT_VF:
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case RISCV::VMFLE_VV:
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case RISCV::VMFLE_VF:
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case RISCV::VMFGT_VF:
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case RISCV::VMFGE_VF:
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return true;
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}
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return false;
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}
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class RISCVVectorMaskDAGMutation : public ScheduleDAGMutation {
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private:
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const TargetRegisterInfo *TRI;
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public:
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RISCVVectorMaskDAGMutation(const TargetRegisterInfo *TRI) : TRI(TRI) {}
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void apply(ScheduleDAGInstrs *DAG) override {
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SUnit *NearestUseV0SU = nullptr;
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for (SUnit &SU : DAG->SUnits) {
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const MachineInstr *MI = SU.getInstr();
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if (MI->findRegisterUseOperand(RISCV::V0, TRI))
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NearestUseV0SU = &SU;
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if (NearestUseV0SU && NearestUseV0SU != &SU && isVectorMaskProducer(MI) &&
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// For LMUL=8 cases, there will be more possibilities to spill.
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// FIXME: We should use RegPressureTracker to do fine-grained
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// controls.
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RISCVII::getLMul(MI->getDesc().TSFlags) != RISCVII::LMUL_8)
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DAG->addEdge(&SU, SDep(NearestUseV0SU, SDep::Artificial));
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}
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}
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};
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std::unique_ptr<ScheduleDAGMutation>
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createRISCVVectorMaskDAGMutation(const TargetRegisterInfo *TRI) {
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return std::make_unique<RISCVVectorMaskDAGMutation>(TRI);
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}
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} // namespace llvm
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