Brox Chen 2b43543afb

[AMDGPU][True16][MC][CodeGen] true16 for v_alignbyte_b32 (#125706) ...

Support true16 format for v_alignbyte_b32 in MC and CodeGen

2025-02-07 09:54:11 -05:00

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AArch64

[AArch64] Add DC CIGDPAPA and DC CIPAPA instructions (#122718)

2025-01-14 08:35:36 +00:00

AMDGPU

[AMDGPU][True16][MC][CodeGen] true16 for v_alignbyte_b32 (#125706)

2025-02-07 09:54:11 -05:00

ARC

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ARM

[llvm-mc] Don't print initial .text for disassembler

2024-12-16 23:38:48 -08:00

Hexagon

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Lanai

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M68k

[M68k] update dissassmbly test to require atLeastM68020 for BSR32 (#119758)

2024-12-12 13:15:43 -08:00

Mips

[test] Don't test initial ".text" in llvm-mc --disassemble output

2024-12-16 23:24:34 -08:00

MSP430

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PowerPC

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RISCV

[RISCV][MC] Create an AsmOperand for carry-in vmask (#124317)

2025-01-24 13:02:33 -08:00

Sparc

[NFC][SPARC] Fix typos and style mismatches

2024-06-19 21:44:48 +07:00

SystemZ

[SystemZ] Add support for new cpu architecture - arch15

2025-01-20 19:30:21 +01:00

WebAssembly

[test] Don't test initial ".text" in llvm-mc --disassemble output

2024-12-16 23:24:34 -08:00

X86

[X86][AVX10.2-BF16] Remove [NE]P from intrinsic and instruction name (#123335)

2025-01-24 15:49:28 +08:00

XCore

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Xtensa

[Xtensa] Implement Windowed Register Option. (#124656)

2025-02-03 03:13:24 +03:00