Oliver Stannard 1f2c36a879

[ARM] Reject fixed-point VCVT with different registers (#126232) ...

These instructions only have one register field in their encoding, so
both registers in the assembly must be the same.

Previously, we were accepting these instructions, but ignoring the
second register operand.

Fixes #126227

2025-02-07 14:32:15 +00:00

..

AArch64

[AArch64] Add mayStore to more store instructions

2025-01-14 11:14:45 +00:00

AMDGPU

AMDGPU: Verify f8f6f4 formats in assembler (#117826)

2024-11-26 23:45:03 -05:00

ARM

[ARM] Reject fixed-point VCVT with different registers (#126232)

2025-02-07 14:32:15 +00:00

JSON/X86

[llvm-mca] Add bottle-neck analysis to JSON output. (#90056)

2024-08-19 17:16:19 +01:00

RISCV

[RISCV] Remove potentially incompatible vtype toggles fro mvlseg-vsseg mca test (#125226)

2025-01-31 19:50:34 -05:00

SystemZ

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X86

[X86] Handle BSF/BSR "zero-input pass through" behaviour (#123623)

2025-01-23 12:59:59 +00:00

invalid_input_file_name.test

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lit.local.cfg

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