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llvm-project/llvm/lib/Target/AArch64
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David Green 509b397dd5 [AArch64] Combine vector fptoi.sat(fmul) to fixed point fcvtz 
Similar to D113199 but dealing with the vector size, this extends the
fptosi+fmul to fixed point fold to handle fptosi.sat nodes that are
equally viable, so long as the saturation width matches the output
width.

Differential Revision: https://reviews.llvm.org/D113200
2021-11-10 16:12:48 +00:00
..
AsmParser
[AArch64] Add support for the 'R' architecture profile.
2021-10-27 12:32:30 +01:00
Disassembler
[aarch64/mac] Correctly disassemble @TLVPPAGE(OFF) relocs
2021-11-10 10:41:18 -05:00
GISel
[AArch64][GlobalISel] Fix atomic truncating stores from generating invalid copies.
2021-11-09 20:47:50 -08:00
MCTargetDesc
[AArch64] Diagnose large adrp offset on Windows.
2021-11-02 15:11:22 -07:00
TargetInfo
Fix shlib builds for all lib/Target/*/TargetInfo libs
2021-10-08 15:21:13 -07:00
Utils
[AArch64] Add support for the 'R' architecture profile.
2021-10-27 12:32:30 +01:00
AArch64.h
Third Recommit "[AArch64] Split bitmask immediate of bitwise AND operation"
2021-10-08 11:28:49 +01:00
AArch64.td
[AArch64] Enablement of Cortex-X2
2021-11-01 11:55:24 +00:00
AArch64A53Fix835769.cpp
[Target] Use llvm::reverse (NFC)
2021-11-06 13:08:21 -07:00
AArch64A57FPLoadBalancing.cpp
…
AArch64AdvSIMDScalarPass.cpp
[AArch64, AMDGPU] Use make_early_inc_range (NFC)
2021-11-03 09:22:51 -07:00
AArch64AsmPrinter.cpp
Move TargetRegistry.(h|cpp) from Support to MC
2021-10-08 14:51:48 -07:00
AArch64BranchTargets.cpp
[AArch64] Fix for BTI landing pad insertion with PAC-RET+bkey.
2021-04-23 10:07:25 +02:00
AArch64CallingConvention.cpp
[clang][AArch64] Correctly align HFA arguments when passed on the stack
2021-04-15 22:58:14 +01:00
AArch64CallingConvention.h
…
AArch64CallingConvention.td
[AArch64] Replace unneeded CCAssignToRegWithShadow with CCAssignToReg
2021-08-21 16:33:29 -07:00
AArch64CleanupLocalDynamicTLSPass.cpp
…
AArch64CollectLOH.cpp
…
AArch64Combine.td
[AArch64][GlobalISel] Change G_ANYEXT fed by scalar G_ICMP to G_ZEXT
2021-10-01 15:01:20 -07:00
AArch64CompressJumpTables.cpp
…
AArch64CondBrTuning.cpp
[CodeGen, Target] Use MachineBasicBlock::terminators (NFC)
2021-10-31 07:57:34 -07:00
AArch64ConditionalCompares.cpp
…
AArch64ConditionOptimizer.cpp
…
AArch64DeadRegisterDefinitionsPass.cpp
…
AArch64ExpandImm.cpp
[AArch64] Fix some coding standard issues related to namespace llvm
2021-05-05 15:27:16 -07:00
AArch64ExpandImm.h
…
AArch64ExpandPseudoInsts.cpp
[Aarch64] Correct register class for pseudo instructions
2021-09-09 14:31:49 -04:00
AArch64FalkorHWPFFix.cpp
…
AArch64FastISel.cpp
[ADT] Add APInt::isNegatedPowerOf2() helper
2021-10-19 14:38:21 +01:00
AArch64FrameLowering.cpp
[Target] Use llvm::reverse (NFC)
2021-11-06 13:08:21 -07:00
AArch64FrameLowering.h
[AArch64] Remove unused declaration hasSwiftExtendedFrame (NFC)
2021-10-31 22:58:56 -07:00
AArch64GenRegisterBankInfo.def
AArch64: support i128 cmpxchg in GlobalISel.
2021-05-14 10:41:38 +01:00
AArch64InstrAtomics.td
[AArch64] Fix i128 cmpxchg using ldxp/stxp.
2021-07-20 12:38:12 -07:00
AArch64InstrFormats.td
[AArch64] Rename some timm predicates for consistency. NFC.
2021-10-28 11:41:29 -07:00
AArch64InstrGISel.td
AArch64: support i128 cmpxchg in GlobalISel.
2021-05-14 10:41:38 +01:00
AArch64InstrInfo.cpp
[NFC][AArch64] Handle processLogicalImmediate error
2021-11-10 16:57:24 +03:00
AArch64InstrInfo.h
[InstrInfo] Use 64-bit immediates for analyzeCompare() (NFCI)
2021-08-30 19:46:04 +02:00
AArch64InstrInfo.td
[AArch64] Combine fptoi.sat(fmul) to fixed point cvtf
2021-11-08 10:07:34 +00:00
AArch64ISelDAGToDAG.cpp
[AArch64][SVE] Use TargetFrameIndex in more SVE load/store addressing modes
2021-10-29 14:44:16 +00:00
AArch64ISelLowering.cpp
[AArch64] Combine vector fptoi.sat(fmul) to fixed point fcvtz
2021-11-10 16:12:48 +00:00
AArch64ISelLowering.h
[AArch64][SVE] Generate SVE >1 element structured load/stores from fixed types
2021-10-29 09:35:57 +00:00
AArch64LoadStoreOptimizer.cpp
AArch64: don't form indexed paired ops if base reg overlaps operands.
2021-08-20 11:39:38 +01:00
AArch64LowerHomogeneousPrologEpilog.cpp
[llvm] Use llvm::is_contained (NFC)
2021-10-14 22:44:09 -07:00
AArch64MachineFunctionInfo.cpp
[llvm] Rename StringRef _lower() method calls to _insensitive()
2021-06-25 00:22:01 +03:00
AArch64MachineFunctionInfo.h
IR/AArch64/X86: add "swifttailcc" calling convention.
2021-05-17 10:48:34 +01:00
AArch64MacroFusion.cpp
[AArch64] Fix some coding standard issues related to namespace llvm
2021-05-05 15:27:16 -07:00
AArch64MacroFusion.h
…
AArch64MCInstLower.cpp
[AArch64][ELF] Prefer to lower MC_GlobalAddress operands to .Lfoo$local
2021-05-07 09:44:26 -07:00
AArch64MCInstLower.h
…
AArch64MIPeepholeOpt.cpp
Revert "[AArch64] Optimize add/sub with immediate"
2021-11-03 14:15:21 +08:00
AArch64PBQPRegAlloc.cpp
[NFCI] Move DEBUG_TYPE definition below #includes
2021-05-30 17:31:01 +08:00
AArch64PBQPRegAlloc.h
…
AArch64PerfectShuffle.h
…
AArch64PfmCounters.td
…
AArch64PromoteConstant.cpp
…
AArch64RedundantCopyElimination.cpp
…
AArch64RegisterBanks.td
AArch64: support i128 cmpxchg in GlobalISel.
2021-05-14 10:41:38 +01:00
AArch64RegisterInfo.cpp
[AArch64][SME] Add load and store instructions
2021-07-16 10:11:10 +00:00
AArch64RegisterInfo.h
…
AArch64RegisterInfo.td
[AArch64][SVE] NFC: Remove unused p0-p7 with element size predicates
2021-08-10 07:56:22 +00:00
AArch64SchedA53.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedA55.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedA57.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedA57WriteRes.td
…
AArch64SchedA64FX.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedCyclone.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedExynosM3.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedExynosM4.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedExynosM5.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedFalkor.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedFalkorDetails.td
…
AArch64SchedKryo.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedKryoDetails.td
…
AArch64SchedPredExynos.td
…
AArch64SchedPredicates.td
…
AArch64SchedThunderX2T99.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedThunderX3T110.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedThunderX.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedTSV110.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64Schedule.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SelectionDAGInfo.cpp
[SelectionDAG] Add isZero/isAllOnes methods to ConstantSDNode.
2021-09-09 13:28:30 -07:00
AArch64SelectionDAGInfo.h
…
AArch64SIMDInstrOpt.cpp
…
AArch64SLSHardening.cpp
[ARM][AArch64] SLSHardening: make non-comdat thunks possible
2021-05-20 17:07:05 +02:00
AArch64SMEInstrInfo.td
[AArch64][SME] Update DUP (predicate) instruction
2021-10-07 08:55:11 +00:00
AArch64SpeculationHardening.cpp
…
AArch64StackTagging.cpp
[hwasan] Support more complicated lifetimes.
2021-09-03 10:29:50 +01:00
AArch64StackTaggingPreRA.cpp
[AArch64, AMDGPU] Use make_early_inc_range (NFC)
2021-11-03 09:22:51 -07:00
AArch64StorePairSuppress.cpp
[AArch64] Disable AArch64StorePairSuppress under optsize
2021-10-04 18:28:15 +01:00
AArch64Subtarget.cpp
[AArch64] Enablement of Cortex-X2
2021-11-01 11:55:24 +00:00
AArch64Subtarget.h
[AArch64] Enablement of Cortex-X2
2021-11-01 11:55:24 +00:00
AArch64SVEInstrInfo.td
[AArch64][SVE] Use TargetFrameIndex in more SVE load/store addressing modes
2021-10-29 14:44:16 +00:00
AArch64SystemOperands.td
[AArch64] Add support for the 'R' architecture profile.
2021-10-27 12:32:30 +01:00
AArch64TargetMachine.cpp
[AArch64] Always add -tune-cpu argument to -cc1 driver
2021-10-19 14:57:51 +01:00
AArch64TargetMachine.h
…
AArch64TargetObjectFile.cpp
…
AArch64TargetObjectFile.h
…
AArch64TargetTransformInfo.cpp
[AArch64][SVE] Combine FADD and FMUL aarch64 intrinsics to FMLA
2021-11-08 12:22:38 +00:00
AArch64TargetTransformInfo.h
[LV] Use VScaleForTuning to fine-tune the cost per lane.
2021-11-08 16:59:46 +00:00
CMakeLists.txt
Third Recommit "[AArch64] Split bitmask immediate of bitwise AND operation"
2021-10-08 11:28:49 +01:00
SMEInstrFormats.td
[AArch64][SME] Update DUP (predicate) instruction
2021-10-07 08:55:11 +00:00
SVEInstrFormats.td
[AArch64] Rename some timm predicates for consistency. NFC.
2021-10-28 11:41:29 -07:00
SVEIntrinsicOpts.cpp
[llvm][clang][NFC] updates inline licence info
2021-08-11 02:48:53 +00:00