eopXD ecbf5db88d [6/15][Clang][RISCV][NFC] Instructions with a mask destination register is always tail agnostic ...

The logic under `computeBuiltinTypes` is an amendment to setting Policy as
`Omit`. The tail policy should be set to agnostic for those intrinsics that
has `HasTailPolicy = false`, which are the intrinsics with a mask destination
register.

This is the 6th commit of a patch-set that aims to change the default policy
for RVV intrinsics from TAMU to TAMA.

Please refer to the cover letter in the 1st commit (D141573) for an
overview.

Reviewed By: craig.topper, kito-cheng

Differential Revision: https://reviews.llvm.org/D141756

2023-01-24 01:08:58 -08:00

..

CMakeLists.txt

clang-tblgen build: avoid duplicate inclusion of libLLVMSupport

2022-10-28 15:48:20 +02:00

RISCVVIntrinsicUtils.cpp

[6/15][Clang][RISCV][NFC] Instructions with a mask destination register is always tail agnostic

2023-01-24 01:08:58 -08:00