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llvm-project/llvm/test/CodeGen
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James Y Knight ed4194bb8d
[X86] Set MaxAtomicSizeInBitsSupported. (#75112) 
This will result in larger atomic operations getting expanded to
`__atomic_*` libcalls via AtomicExpandPass, which matches what Clang
already does in the frontend.
2023-12-12 08:16:55 -05:00
..
AArch64
[AArch64]: Added code for generating XAR instruction (#75085)
2023-12-12 05:48:45 +00:00
AMDGPU
[AMDGPU] Update VOP instructions for GFX12 (#74853)
2023-12-12 11:38:24 +01:00
ARC
…
ARM
[CodeGen] Port SjLjEHPrepare to new pass manager (#75023)
2023-12-12 16:07:26 +08:00
AVR
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
BPF
[BPF][GlobalISel] select non-PreISelGenericOpcode (#75034)
2023-12-12 16:19:34 +08:00
CSKY
[CSKY,test] Update switch.ll
2023-10-31 15:47:05 -07:00
DirectX
[DirectX] Move ROV info into HLSL metadata. NFC
2023-12-09 10:42:45 -08:00
Generic
[CodeGen] Update DwarfEHPreparePass references in CodeGenPassBuilder.h (#74068)
2023-12-11 09:26:01 +08:00
Hexagon
[Tests] Add disjoint flag to some tests (NFC)
2023-12-05 14:09:36 +01:00
Inputs
…
Lanai
…
LoongArch
[LoongArch] Add codegen support for [X]VF{MSUB/NMADD/NMSUB}.{S/D} instructions (#74819)
2023-12-11 10:37:22 +08:00
M68k
[M68k] Emit RTE for interrupt handler. (#72787)
2023-12-04 15:11:00 +08:00
Mips
[CodeGen] Update DwarfEHPreparePass references in CodeGenPassBuilder.h (#74068)
2023-12-11 09:26:01 +08:00
MIR
MachineVerifier: Reject extra non-register operands on instructions (#73758)
2023-11-30 22:33:42 +09:00
MLRegAlloc
[mlgo] Fix test post PR #73899
2023-12-01 09:05:22 -08:00
MSP430
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
NVPTX
[NVPTX] Custom lower integer<->bf16 conversions for sm_80 (#74827)
2023-12-11 21:06:46 +01:00
PowerPC
[MachinePipeliner] Fix store-store dependences (#72575)
2023-12-11 21:10:34 -06:00
RISCV
[RISCV] Move test to RVV directory. NFC
2023-12-12 17:31:59 +09:00
SPARC
[Sparc] Remove duplicate ALU and SETHI instructions (NFCI) (#66851)
2023-10-10 20:34:20 +03:00
SPIRV
[SPIR-V] Fixup tests (#73371)
2023-12-07 15:23:27 -05:00
SystemZ
[SystemZ] Use LCGR/AGHI for i64 XOR with -1 (#74882)
2023-12-11 17:28:12 +01:00
Thumb
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
Thumb2
[SCEVExpander] Attempt to reinfer flags dropped due to CSE (#72431)
2023-12-07 13:20:36 -08:00
VE
BlockFrequencyInfoImpl: Avoid big numbers, increase precision for small spreads
2023-10-24 20:27:39 -07:00
WebAssembly
[CodeGen] Rename winehprepare -> win-eh-prepare (#75024)
2023-12-11 13:55:27 +08:00
WinCFGuard
…
WinEH
[CodeGen] Rename winehprepare -> win-eh-prepare (#75024)
2023-12-11 13:55:27 +08:00
X86
[X86] Set MaxAtomicSizeInBitsSupported. (#75112)
2023-12-12 08:16:55 -05:00
XCore
[XCore] Set MaxAtomicSizeInBitsSupported to 0 (#74389)
2023-12-05 12:51:01 -05:00