Ramkumar Ramachandra ef023cae38

Reland [VPlan] Expand WidenInt inductions with nuw/nsw (#168354) ...

Changes: The previous patch had to be reverted to a mismatching-OpType
assert in cse. The reduced-test has now been added corresponding to a
RVV pointer-induction, and the pointer-induction case has been updated
to use createOverflowingBinaryOp.

While at it, record VPIRFlags in VPWidenInductionRecipe.

2025-11-17 13:44:25 +00:00

..

bf16.ll

[VPlan] Remove original loop blocks if dead. (#155497)

2025-10-01 16:53:59 +00:00

blend-any-of-reduction-cost.ll

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blocks-with-dead-instructions.ll

Reland [VPlan] Expand WidenInt inductions with nuw/nsw (#168354)

2025-11-17 13:44:25 +00:00

dead-ops-cost.ll

Reland [VPlan] Expand WidenInt inductions with nuw/nsw (#168354)

2025-11-17 13:44:25 +00:00

defaults.ll

[VPlan] Remove original loop blocks if dead. (#155497)

2025-10-01 16:53:59 +00:00

divrem.ll

Revert "[LV] Use ExtractLane(LastActiveLane, V) live outs when tail-folding. (#149042)"

2025-11-13 22:34:55 +00:00

evl-compatible-loops.ll

Reland [VPlan] Expand WidenInt inductions with nuw/nsw (#168354)

2025-11-17 13:44:25 +00:00

f16.ll

[VPlan] Remove original loop blocks if dead. (#155497)

2025-10-01 16:53:59 +00:00

first-order-recurrence-scalable-vf1.ll

Revert "[LV] Use ExtractLane(LastActiveLane, V) live outs when tail-folding. (#149042)"

2025-11-13 22:34:55 +00:00

fminimumnum.ll

[LV][EVL] Remove metadata on EVL vectorized loops (#155760)

2025-09-23 07:39:33 +08:00

force-vect-msg.ll

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gather-scatter-cost.ll

Revert "[VPlan] Handle WidenGEP in narrowToSingleScalars" (#167509)

2025-11-11 14:29:28 +00:00

illegal-type.ll

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induction-costs.ll

[VPlan] Remove original loop blocks if dead. (#155497)

2025-10-01 16:53:59 +00:00

inloop-reduction.ll

[VPlan] Remove original loop blocks if dead. (#155497)

2025-10-01 16:53:59 +00:00

interleaved-accesses-zve32x.ll

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interleaved-accesses.ll

[VPlan] Remove original loop blocks if dead. (#155497)

2025-10-01 16:53:59 +00:00

interleaved-cost.ll

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interleaved-masked-access.ll

Reland [VPlan] Expand WidenInt inductions with nuw/nsw (#168354)

2025-11-17 13:44:25 +00:00

interleaved-store-with-gap.ll

Reland [VPlan] Expand WidenInt inductions with nuw/nsw (#168354)

2025-11-17 13:44:25 +00:00

lit.local.cfg

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lmul.ll

[VPlan] Remove original loop blocks if dead. (#155497)

2025-10-01 16:53:59 +00:00

low-trip-count.ll

[VPlan] Simplify ExplicitVectorLength(%AVL) -> %AVL when AVL <= VF (#167647)

2025-11-13 13:17:01 +00:00

mask-index-type.ll

Reland [VPlan] Expand WidenInt inductions with nuw/nsw (#168354)

2025-11-17 13:44:25 +00:00

masked_gather_scatter.ll

Reland [VPlan] Expand WidenInt inductions with nuw/nsw (#168354)

2025-11-17 13:44:25 +00:00

only-compute-cost-for-vplan-vfs.ll

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ordered-reduction.ll

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partial-reduce-dot-product.ll

[VPlan] Disable partial reductions again with EVL tail folding (#167863)

2025-11-14 06:30:12 +00:00

pointer-induction.ll

Reland [VPlan] Expand WidenInt inductions with nuw/nsw (#168354)

2025-11-17 13:44:25 +00:00

pr87378-vpinstruction-or-drop-poison-generating-flags.ll

[VPlan] Remove original loop blocks if dead. (#155497)

2025-10-01 16:53:59 +00:00

pr88802.ll

[VPlan] Remove original loop blocks if dead. (#155497)

2025-10-01 16:53:59 +00:00

pr154103.ll

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preserve-dbg-loc.ll

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reductions.ll

[VPlan] Remove original loop blocks if dead. (#155497)

2025-10-01 16:53:59 +00:00

reg-usage-bf16.ll

[VPlan] Always consider register pressure on RISC-V (#156951)

2025-09-12 06:21:54 +00:00

reg-usage-f16.ll

[VPlan] Always consider register pressure on RISC-V (#156951)

2025-09-12 06:21:54 +00:00

reg-usage-maxbandwidth.ll

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reg-usage-prune-vf.ll

[VPlan] Remove original loop blocks if dead. (#155497)

2025-10-01 16:53:59 +00:00

reg-usage.ll

[VPlan] Always consider register pressure on RISC-V (#156951)

2025-09-12 06:21:54 +00:00

remark-reductions.ll

[VPlan] Remove original loop blocks if dead. (#155497)

2025-10-01 16:53:59 +00:00

riscv-interleaved.ll

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riscv-unroll.ll

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riscv-vector-reverse.ll

[VPlan] Add VPInstruction to unpack vector values to scalars. (#155670)

2025-10-19 18:49:05 +00:00

safe-dep-distance.ll

Reland [VPlan] Expand WidenInt inductions with nuw/nsw (#168354)

2025-11-17 13:44:25 +00:00

scalable-basics.ll

[VPlan] Remove original loop blocks if dead. (#155497)

2025-10-01 16:53:59 +00:00

scalable-tailfold.ll

Revert "[LV] Use ExtractLane(LastActiveLane, V) live outs when tail-folding. (#149042)"

2025-11-13 22:34:55 +00:00

scalable-vf-hint.ll

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select-cmp-reduction.ll

[VPlan] Remove original loop blocks if dead. (#155497)

2025-10-01 16:53:59 +00:00

select-invariant-cond-cost.ll

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short-trip-count.ll

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strided-accesses.ll

Reland [VPlan] Expand WidenInt inductions with nuw/nsw (#168354)

2025-11-17 13:44:25 +00:00

tail-folding-bin-unary-ops-args.ll

[LV][EVL] Remove metadata on EVL vectorized loops (#155760)

2025-09-23 07:39:33 +08:00

tail-folding-call-intrinsics.ll

[LV][EVL] Remove metadata on EVL vectorized loops (#155760)

2025-09-23 07:39:33 +08:00

tail-folding-cast-intrinsics.ll

Reland [VPlan] Expand WidenInt inductions with nuw/nsw (#168354)

2025-11-17 13:44:25 +00:00

tail-folding-cond-reduction.ll

Reland [VPlan] Expand WidenInt inductions with nuw/nsw (#168354)

2025-11-17 13:44:25 +00:00

tail-folding-cost.ll

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tail-folding-div.ll

[VPlan] Remove original loop blocks if dead. (#155497)

2025-10-01 16:53:59 +00:00

tail-folding-fixed-order-recurrence.ll

Reland [VPlan] Expand WidenInt inductions with nuw/nsw (#168354)

2025-11-17 13:44:25 +00:00

tail-folding-gather-scatter.ll

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tail-folding-inloop-reduction.ll

[VPlan] Remove original loop blocks if dead. (#155497)

2025-10-01 16:53:59 +00:00

tail-folding-interleave.ll

Reland [VPlan] Expand WidenInt inductions with nuw/nsw (#168354)

2025-11-17 13:44:25 +00:00

tail-folding-intermediate-store.ll

[LV][EVL] Remove metadata on EVL vectorized loops (#155760)

2025-09-23 07:39:33 +08:00

tail-folding-iv32.ll

[VPlan] Remove original loop blocks if dead. (#155497)

2025-10-01 16:53:59 +00:00

tail-folding-known-no-overflow.ll

[VPlan] Remove original loop blocks if dead. (#155497)

2025-10-01 16:53:59 +00:00

tail-folding-masked-loadstore.ll

[IR] Replace alignment argument with attribute on masked intrinsics (#163802)

2025-10-20 08:50:09 +00:00

tail-folding-no-masking.ll

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tail-folding-ordered-reduction.ll

[VPlan] Remove original loop blocks if dead. (#155497)

2025-10-01 16:53:59 +00:00

tail-folding-reduction-cost.ll

…

tail-folding-reduction.ll

[VPlan] Remove original loop blocks if dead. (#155497)

2025-10-01 16:53:59 +00:00

tail-folding-reverse-load-store.ll

[IR] Replace alignment argument with attribute on masked intrinsics (#163802)

2025-10-20 08:50:09 +00:00

tail-folding-safe-dep-distance.ll

[VPlan] Remove original loop blocks if dead. (#155497)

2025-10-01 16:53:59 +00:00

tail-folding-uniform-store.ll

[VPlan] Remove original loop blocks if dead. (#155497)

2025-10-01 16:53:59 +00:00

transform-narrow-interleave-to-widen-memory.ll

[VPlan] Plumb scalable register size through narrowInterleaveGroups (#167505)

2025-11-12 11:14:53 +00:00

truncate-to-minimal-bitwidth-cost.ll

[LV] Check for TruncInsts in canTruncateToMinimalBitwidth.

2025-10-20 22:31:16 +01:00

truncate-to-minimal-bitwidth-evl-crash.ll

[VPlan] Set flags when constructing truncs using VPWidenCastRecipe.

2025-10-12 14:01:12 +01:00

type-info-cache-evl-crash.ll

[LV][EVL] Remove metadata on EVL vectorized loops (#155760)

2025-09-23 07:39:33 +08:00

uniform-load-store.ll

Reland [VPlan] Expand WidenInt inductions with nuw/nsw (#168354)

2025-11-17 13:44:25 +00:00

unroll-in-loop-vectorizer.ll

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veclib-function-calls.ll

[IR] Mark vector intrinsics speculatable (#162334)

2025-10-09 09:41:59 +01:00

vector-loop-backedge-elimination-with-evl.ll

[VPlan] Simplify ExplicitVectorLength(%AVL) -> %AVL when AVL <= VF (#167647)

2025-11-13 13:17:01 +00:00

vectorize-vp-intrinsics.ll

[VPlan] Remove original loop blocks if dead. (#155497)

2025-10-01 16:53:59 +00:00

vf-will-not-generate-any-vector-insts.ll

[LV][EVL] Remove metadata on EVL vectorized loops (#155760)

2025-09-23 07:39:33 +08:00

vplan-riscv-vector-reverse.ll

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vplan-vp-intrinsics-fixed-order-recurrence.ll

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vplan-vp-intrinsics-reduction.ll

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vplan-vp-intrinsics.ll

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zvl32b.ll

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