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llvm-project/llvm/test/CodeGen/MIR/X86
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Roman Lebedev 564d85e090
The maximal representable alignment in LLVM IR is 1GiB, not 512MiB 
In LLVM IR, `AlignmentBitfieldElementT` is 5-bit wide
But that means that the maximal alignment exponent is `(1<<5)-2`,
which is `30`, not `29`. And indeed, alignment of `1073741824`
roundtrips IR serialization-deserialization.

While this doesn't seem all that important, this doubles
the maximal supported alignment from 512MiB to 1GiB,
and there's actually one noticeable use-case for that;
On X86, the huge pages can have sizes of 2MiB and 1GiB (!).

So while this doesn't add support for truly huge alignments,
which i think we can easily-ish do if wanted, i think this adds
zero-cost support for a not-trivially-dismissable case.

I don't believe we need any upgrade infrastructure,
and since we don't explicitly record the IR version,
we don't need to bump one either.

As @craig.topper speculates in D108661#2963519,
this might be an artificial limit imposed by the original implementation
of the `getAlignment()` functions.

Differential Revision: https://reviews.llvm.org/D108661
2021-08-26 12:53:39 +03:00
..
auto-successor.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
basic-block-liveins.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
basic-block-not-at-start-of-line-error.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
block-address-operands.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
branch-folder-with-debug.mir
[BranchFolding] skip debug instr to avoid code change
2019-10-29 11:45:38 +00:00
branch-folder-with-label.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
branch-probabilities.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
call-site-info-error1.mir
Revert "Reland "[DebugInfo] Enable the debug entry values feature by default""
2020-02-20 14:41:39 +01:00
call-site-info-error2.mir
Revert "Reland "[DebugInfo] Enable the debug entry values feature by default""
2020-02-20 14:41:39 +01:00
call-site-info-error3.mir
Revert "Reland "[DebugInfo] Enable the debug entry values feature by default""
2020-02-20 14:41:39 +01:00
call-site-info-error4.mir
Reland D73534: [DebugInfo] Enable the debug entry values feature by default
2020-03-19 13:57:30 +01:00
callee-saved-info.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
cfi-def-cfa-offset.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
cfi-def-cfa-register.mir
Migrate function attribute "no-frame-pointer-elim" to "frame-pointer"="all" as cleanups after D56351
2019-12-24 15:57:33 -08:00
cfi-offset.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
constant-pool-item-redefinition-error.mir
…
constant-pool.mir
[X86] Model MXCSR for all SSE instructions
2019-10-30 15:07:49 -07:00
constant-value-error.mir
…
copyIRflags.mir
add IR flags to MI
2018-09-11 21:35:32 +00:00
dbg-value-list.mir
Reapply "[DebugInfo] Add new instruction and DIExpression operator for variadic debug values"
2021-03-05 12:32:05 +00:00
dead-register-flag.mir
Migrate function attribute "no-frame-pointer-elim"="false" to "frame-pointer"="none" as cleanups after D56351
2019-12-24 16:27:51 -08:00
def-register-already-tied-error.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
diexpr-win32.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
duplicate-memory-operand-flag.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
duplicate-register-flag-error.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
early-clobber-register-flag.mir
[MIR] Add comments to INLINEASM immediate flag MachineOperands
2020-04-16 13:46:14 +02:00
empty0.mir
Add triples or specify REQUIRES: default_triple to some tests
2018-01-27 23:31:09 +00:00
empty1.mir
Add triples or specify REQUIRES: default_triple to some tests
2018-01-27 23:31:09 +00:00
empty2.mir
Add triples or specify REQUIRES: default_triple to some tests
2018-01-27 23:31:09 +00:00
escape-function-name.ll
[YAML] Add support for non-printable characters
2017-12-18 17:38:03 +00:00
expected-align-in-memory-operand.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
expected-alignment-after-align-in-memory-operand.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
expected-basic-block-at-start-of-body.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
expected-block-reference-in-blockaddress.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
expected-comma-after-cfi-register.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
expected-comma-after-memory-operand.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
expected-different-implicit-operand.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
expected-different-implicit-register-flag.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
expected-function-reference-after-blockaddress.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
expected-global-value-after-blockaddress.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
expected-integer-after-offset-sign.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
expected-integer-after-tied-def.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
expected-integer-in-successor-weight.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
expected-load-or-store-in-memory-operand.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
expected-machine-operand.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
expected-metadata-node-after-debug-location.mir
Migrate function attribute "no-frame-pointer-elim"="false" to "frame-pointer"="none" as cleanups after D56351
2019-12-24 16:27:51 -08:00
expected-metadata-node-after-exclaim.mir
Migrate function attribute "no-frame-pointer-elim"="false" to "frame-pointer"="none" as cleanups after D56351
2019-12-24 16:27:51 -08:00
expected-metadata-node-in-stack-object.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
expected-named-register-in-allocation-hint.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
expected-named-register-in-callee-saved-register.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
expected-named-register-in-functions-livein.mir
…
expected-named-register-livein.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
expected-newline-at-end-of-list.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
expected-number-after-bb.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
expected-offset-after-cfi-operand.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
expected-pointer-value-in-memory-operand.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
expected-positive-alignment-after-align.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
expected-power-of-2-after-align.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
expected-register-after-cfi-operand.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
expected-register-after-flags.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
expected-size-integer-after-memory-operation2.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
expected-size-integer-after-memory-operation.mir
Consistently use MemoryLocation::UnknownSize to indicate unknown access size
2018-08-20 20:37:57 +00:00
expected-stack-object.mir
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
2019-09-11 11:16:48 +00:00
expected-subregister-after-colon.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
expected-target-flag-name.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
expected-tied-def-after-lparen.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
expected-value-in-memory-operand.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
expected-virtual-register-in-functions-livein.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
external-symbol-operands.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
fastmath.mir
[X86] Model MXCSR for all SSE instructions
2019-10-30 15:07:49 -07:00
fixed-stack-di.mir
OpaquePtr: Bulk update tests to use typed byval
2020-11-20 14:00:46 -05:00
fixed-stack-memory-operands.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
fixed-stack-object-redefinition-error.mir
Migrate function attribute "no-frame-pointer-elim"="false" to "frame-pointer"="none" as cleanups after D56351
2019-12-24 16:27:51 -08:00
fixed-stack-objects.mir
Migrate function attribute "no-frame-pointer-elim"="false" to "frame-pointer"="none" as cleanups after D56351
2019-12-24 16:27:51 -08:00
frame-info-save-restore-points.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
frame-info-stack-references.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
frame-setup-instruction-flag.mir
[MIR] Allow frame-setup and frame-destroy on the same instruction
2018-03-13 19:53:16 +00:00
function-liveins.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
generic-instr-type.mir
[Test] Tidy up loose ends from LLVM_HAS_GLOBAL_ISEL
2020-08-27 16:36:27 +01:00
global-value-operands.mir
Print quoted backslashes in LLVM IR as \\ instead of \5C
2019-10-10 18:31:57 +00:00
immediate-operands.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
implicit-register-flag.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
inline-asm-registers.mir
[X86] AVX512FP16 instructions enabling 1/6
2021-08-10 12:46:01 +08:00
inline-asm.mir
[MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'.
2018-01-10 00:56:48 +00:00
instr-heap-alloc-operands.mir
[MIR] Add MIR parsing for heap alloc site instruction markers
2019-11-05 12:57:45 -08:00
instr-symbols-and-mcsymbol-operands.mir
[x86/MIR] Implement support for pre- and post-instruction symbols, as
2018-08-16 23:11:05 +00:00
instructions-debug-location.mir
[MachineVerifier] Verify that a DBG_VALUE has a debug location
2020-05-28 13:53:40 -07:00
invalid-constant-pool-item.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
invalid-debug-location.mir
MIRParser: Check that instructions only reference DILocation metadata
2018-10-01 17:50:52 +00:00
invalid-metadata-node-type.mir
[MIR] Add support for debug metadata for fixed stack objects
2018-04-25 18:58:06 +00:00
invalid-target-flag-name.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
invalid-tied-def-index-error.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
jump-table-info.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
jump-table-redefinition-error.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
killed-register-flag.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
large-cfi-offset-number-error.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
large-immediate-operand-error.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
large-index-number-error.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
large-offset-number-error.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
large-size-in-memory-operand-error.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
lit.local.cfg
…
liveout-register-mask.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
load-with-1gb-alignment.mir
The maximal representable alignment in LLVM IR is 1GiB, not 512MiB
2021-08-26 12:53:39 +03:00
machine-basic-block-operands.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
machine-instructions.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
machine-metadata-error.mir
[MIRParser] Add machine metadata.
2021-06-28 22:29:36 -04:00
machine-metadata.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
machine-verifier.mir
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
memory-operands.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
metadata-operands.mir
[MachineVerifier] Verify that a DBG_VALUE has a debug location
2020-05-28 13:53:40 -07:00
mir-canon-hash-bb.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
mir-namer-hash-frameindex.mir
[MIRVRegNamer] Experimental MachineInstr stable hashing (Fowler-Noll-Vo)
2020-09-03 16:13:09 -04:00
mircanon-flags.mir
[MIRVRegNamer] Experimental MachineInstr stable hashing (Fowler-Noll-Vo)
2020-09-03 16:13:09 -04:00
missing-closing-quote.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
missing-comma.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
missing-implicit-operand.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
named-registers.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
newline-handling.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
null-register-operands.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
pr38773.mir
[DebugInfo] MCP: collect and update DBG_VALUEs encountered in local block
2019-08-14 12:20:02 +00:00
register-mask-operands.mir
Migrate function attribute "no-frame-pointer-elim"="false" to "frame-pointer"="none" as cleanups after D56351
2019-12-24 16:27:51 -08:00
register-operand-class-invalid0.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
register-operand-class-invalid1.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
register-operand-class.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
register-operands-target-flag-error.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
renamable-register-flag.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
roundtrip.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
simple-register-allocation-hints.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
spill-slot-fixed-stack-object-aliased.mir
[YAML] Use correct source location for unknown key errors.
2020-12-11 16:34:06 +00:00
spill-slot-fixed-stack-object-immutable.mir
[YAML] Use correct source location for unknown key errors.
2020-12-11 16:34:06 +00:00
spill-slot-fixed-stack-objects.mir
Migrate function attribute "no-frame-pointer-elim"="false" to "frame-pointer"="none" as cleanups after D56351
2019-12-24 16:27:51 -08:00
stack-object-debug-info.mir
[MIR] Add support for debug metadata for fixed stack objects
2018-04-25 18:58:06 +00:00
stack-object-invalid-name.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
stack-object-operand-name-mismatch-error.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
stack-object-operands.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
stack-object-redefinition-error.mir
Migrate function attribute "no-frame-pointer-elim"="false" to "frame-pointer"="none" as cleanups after D56351
2019-12-24 16:27:51 -08:00
stack-objects.mir
Migrate function attribute "no-frame-pointer-elim"="false" to "frame-pointer"="none" as cleanups after D56351
2019-12-24 16:27:51 -08:00
standalone-register-error.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
subreg-on-physreg.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
subregister-index-operands.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
subregister-operands.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
successor-basic-blocks-weights.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
successor-basic-blocks.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
tied-def-operand-invalid.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
tied-physical-regs-match.mir
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
undef-register-flag.mir
Migrate function attribute "no-frame-pointer-elim"="false" to "frame-pointer"="none" as cleanups after D56351
2019-12-24 16:27:51 -08:00
undefined-fixed-stack-object.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
undefined-global-value.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
undefined-ir-block-in-blockaddress.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
undefined-ir-block-slot-in-blockaddress.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
undefined-jump-table-id.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
undefined-named-global-value.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
undefined-register-class.mir
…
undefined-stack-object.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
undefined-value-in-memory-operand.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
undefined-virtual-register.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
unexpected-type-phys.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
unknown-instruction.mir
…
unknown-machine-basic-block.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
unknown-metadata-keyword.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
unknown-metadata-node.mir
Migrate function attribute "no-frame-pointer-elim"="false" to "frame-pointer"="none" as cleanups after D56351
2019-12-24 16:27:51 -08:00
unknown-named-machine-basic-block.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
unknown-register.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
unknown-subregister-index-op.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
unknown-subregister-index.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
unreachable_block.ll
[MIRPrinter] Print empty successor lists when they cannot be guessed
2017-09-19 23:34:12 +00:00
unrecognized-character.mir
…
variable-sized-stack-object-size-error.mir
[YAML] Use correct source location for unknown key errors.
2020-12-11 16:34:06 +00:00
variable-sized-stack-objects.mir
Describe stack-id as an enum
2019-06-17 09:13:29 +00:00
virtual-register-redefinition-error.mir
…
virtual-registers.mir
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
2019-04-05 19:28:09 +00:00
zero-probability.mir
Add 'REQUIRES: default_triple' to test/CodeGen/MIR/X86/zero-probability.mir
2018-11-07 23:33:55 +00:00