Zakk Chen d224be3b99 [RISCV] Add the policy operand for some masked RVV ternary IR intrinsics. ...

Masked reduction intrinsics are specical cases which don't need to have policy
operand. The mask only affects which elements are read. It doesn't effect the
destination register.
The reduction intrinsics have a dedicated destination operand. If it
is undef, we use tail agnostic. If it not undef we use tail
undisturbed.

Co-Authored-by: Craig Topper <craig.topper@sifive.com>

Differential Revision: https://reviews.llvm.org/D117681

2022-02-11 05:02:03 -08:00

..

llvm

[RISCV] Add the policy operand for some masked RVV ternary IR intrinsics.

2022-02-11 05:02:03 -08:00

llvm-c

Add missing includes after LLVMCore header cleanup

2022-02-02 07:51:13 +01:00