89 lines
2.7 KiB
TableGen
89 lines
2.7 KiB
TableGen
//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces which we are implementing
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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include "ARMFeatures.td"
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include "ARMArchitectures.td"
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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include "ARMRegisterInfo.td"
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include "ARMRegisterBanks.td"
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include "ARMCallingConv.td"
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//===----------------------------------------------------------------------===//
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// ARM schedules.
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//===----------------------------------------------------------------------===//
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//
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include "ARMPredicates.td"
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include "ARMSchedule.td"
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//===----------------------------------------------------------------------===//
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// Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "ARMInstrInfo.td"
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def ARMInstrInfo : InstrInfo;
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//===----------------------------------------------------------------------===//
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// ARM schedules
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//
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include "ARMScheduleV6.td"
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include "ARMScheduleA8.td"
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include "ARMScheduleA9.td"
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include "ARMScheduleSwift.td"
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include "ARMScheduleR52.td"
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include "ARMScheduleA57.td"
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include "ARMScheduleM4.td"
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include "ARMScheduleM55.td"
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include "ARMScheduleM7.td"
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include "ARMScheduleM85.td"
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include "ARMProcessors.td"
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//===----------------------------------------------------------------------===//
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// Declare the target which we are implementing
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//===----------------------------------------------------------------------===//
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def ARMAsmWriter : AsmWriter {
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string AsmWriterClassName = "InstPrinter";
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int PassSubtarget = 1;
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int Variant = 0;
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bit isMCAsmWriter = 1;
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}
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def ARMAsmParser : AsmParser {
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bit ReportMultipleNearMisses = 1;
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let PreferSmallerInstructions = true;
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}
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def ARMAsmParserVariant : AsmParserVariant {
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int Variant = 0;
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string Name = "ARM";
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string BreakCharacters = ".";
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}
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def ARM : Target {
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// Pull in Instruction Info.
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let InstructionSet = ARMInstrInfo;
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let AssemblyWriters = [ARMAsmWriter];
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let AssemblyParsers = [ARMAsmParser];
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let AssemblyParserVariants = [ARMAsmParserVariant];
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let AllowRegisterRenaming = 1;
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}
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