4ad517e6b0
CSKY arch has multiple FPU instruction versions such as FPU, FPUv2 and FPUv3 to implement floating operations. For now, we just only support FPUv2 and FPUv3. It includes the encoding, asm parsing of instructions and codegen of DAG nodes.
275 lines
10 KiB
TableGen
275 lines
10 KiB
TableGen
//===- CSKYInstrFormatsF1.td - CSKY Float1.0 Instr Format --*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// CSKY Instruction Format Float1.0 Definitions.
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//
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//===----------------------------------------------------------------------===//
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class CSKYFP1Inst<dag outs, dag ins, string asmstr, list<dag> pattern>
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: CSKY32Inst<AddrModeNone, 0x3d, outs, ins, asmstr, pattern>, Requires<[HasFPUv2_SF]> {
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}
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class F_XYZ_BASE<bits<5> datatype, bits<6> sop, dag outs, dag ins, string opcodestr, list<dag> pattern>
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: CSKYFP1Inst<outs, ins, opcodestr, pattern> {
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bits<4> vrx;
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bits<4> vry;
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bits<4> vrz;
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let Inst{25 - 21} = {0, vry};
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let Inst{20 - 16} = {0, vrx};
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let Inst{15 - 11} = datatype;
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let Inst{10 - 5} = sop;
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let Inst{4 - 0} = {0, vrz};
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}
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class F_XZ_GF<bits<5> datatype, bits<6> sop, dag outs, dag ins, string opcodestr, list<dag> pattern>
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: CSKYFP1Inst<outs, ins, opcodestr, pattern> {
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bits<4> vrx;
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bits<5> rz;
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let Inst{25 - 21} = 0;
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let Inst{20 - 16} = {0, vrx};
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let Inst{15 - 11} = datatype;
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let Inst{10 - 5} = sop;
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let Inst{4 - 0} = {rz};
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}
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class F_XZ_FG<bits<5> datatype, bits<6> sop, dag outs, dag ins, string opcodestr, list<dag> pattern>
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: CSKYFP1Inst<outs, ins, opcodestr, pattern> {
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bits<5> rx;
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bits<4> vrz;
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let Inst{25 - 21} = 0;
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let Inst{20 - 16} = {rx};
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let Inst{15 - 11} = datatype;
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let Inst{10 - 5} = sop;
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let Inst{4 - 0} = {0, vrz};
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}
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class F_XZ_TRANS_FROM<bits<6> sop, string op, RegisterOperand regtype1, RegisterOperand regtype2>
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: F_XZ_GF<3, sop, (outs regtype1:$rz), (ins regtype2:$vrx), !strconcat(op, "\t$rz, $vrx"),
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[]>;
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class F_XZ_TRANS_TO<bits<6> sop, string op, RegisterOperand regtype1, RegisterOperand regtype2>
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: F_XZ_FG<3, sop, (outs regtype1:$vrz), (ins regtype2:$rx), !strconcat(op, "\t$vrz, $rx"),
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[]>;
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let vry = 0 in {
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class F_XZ<bits<5> datatype, bits<6> sop, string op, string op_su, PatFrag opnode, RegisterOperand regtype>
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: F_XYZ_BASE<datatype, sop, (outs regtype:$vrz), (ins regtype:$vrx), !strconcat(op#op_su, "\t$vrz, $vrx"),
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[(set regtype:$vrz, (opnode regtype:$vrx))]>;
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class F_MOV<bits<5> datatype, bits<6> sop, string op, string op_su, RegisterOperand regtype>
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: F_XYZ_BASE<datatype, sop, (outs regtype:$vrz), (ins regtype:$vrx), !strconcat(op#op_su, "\t$vrz, $vrx"),
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[]>;
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class F_XZ_TRANS<bits<6> sop, string op, RegisterOperand regtype1, RegisterOperand regtype2>
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: F_XYZ_BASE<3, sop, (outs regtype1:$vrz), (ins regtype2:$vrx), !strconcat(op, "\t$vrz, $vrx"),
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[]>;
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class F_XZ_TRANS_DS<bits<6> sop, string op, PatFrag opnode>
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: F_XYZ_BASE<3, sop, (outs sFPR32Op:$vrz), (ins sFPR64Op:$vrx), !strconcat(op, "\t$vrz, $vrx"),
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[(set sFPR32Op:$vrz, (opnode sFPR64Op:$vrx))]>;
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class F_XZ_TRANS_SD<bits<6> sop, string op, PatFrag opnode>
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: F_XYZ_BASE<3, sop, (outs sFPR64Op:$vrz), (ins sFPR32Op:$vrx), !strconcat(op, "\t$vrz, $vrx"),
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[(set sFPR64Op:$vrz, (opnode sFPR32Op:$vrx))]>;
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}
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multiclass FT_MOV<bits<6> sop, string op> {
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def _S : F_MOV<0, sop, op, "s", sFPR32Op>;
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let Predicates = [HasFPUv2_DF] in
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def _D : F_MOV<1, sop, op, "d", sFPR64Op>;
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}
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multiclass FT_XZ<bits<6> sop, string op, PatFrag opnode> {
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def _S : F_XZ<0, sop, op, "s", opnode, sFPR32Op>;
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let Predicates = [HasFPUv2_DF] in
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def _D : F_XZ<1, sop, op, "d", opnode, sFPR64Op>;
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}
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let vrz = 0, isCompare = 1 in {
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class F_CMPXY<bits<5> datatype, bits<6> sop, string op, string op_su, RegisterOperand regtype>
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: F_XYZ_BASE<datatype, sop, (outs CARRY:$ca), (ins regtype:$vrx, regtype:$vry), !strconcat(op#op_su, "\t$vrx, $vry"),
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[]>;
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let vry = 0 in{
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class F_CMPZX<bits<5> datatype, bits<6> sop, string op, string op_su, RegisterOperand regtype>
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: F_XYZ_BASE<datatype, sop, (outs CARRY:$ca), (ins regtype:$vrx), !strconcat(op#op_su, "\t$vrx"),
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[]>;
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}
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}
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class F_XYZ<bits<5> datatype, bits<6> sop, string op, string op_su, PatFrag opnode, RegisterOperand regtype>
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: F_XYZ_BASE<datatype, sop, (outs regtype:$vrz), (ins regtype:$vrx, regtype:$vry),
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!strconcat(op#op_su, "\t$vrz, $vrx, $vry"),
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[(set regtype:$vrz, (opnode regtype:$vrx, regtype:$vry))]>;
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multiclass FT_XYZ<bits<6> sop, string op, PatFrag opnode> {
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def _S : F_XYZ<0, sop, op, "s", opnode, sFPR32Op>;
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let Predicates = [HasFPUv2_DF] in
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def _D : F_XYZ<1, sop, op, "d", opnode, sFPR64Op>;
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}
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let Constraints = "$vrt = $vrz" in {
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class F_ACCUM_XYZ<bits<5> datatype, bits<6> sop, string op, string op_su, PatFrag opnode, RegisterOperand regtype>
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: F_XYZ_BASE<datatype, sop, (outs regtype:$vrz), (ins regtype:$vrt, regtype:$vrx, regtype:$vry),
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!strconcat(op#op_su, "\t$vrz, $vrx, $vry"),
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[(set regtype:$vrz, (opnode regtype:$vrt, regtype:$vrx, regtype:$vry))]>;
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}
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multiclass FT_ACCUM_XYZ<bits<6> sop, string op, PatFrag opnode> {
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def _S : F_ACCUM_XYZ<0, sop, op, "s", opnode, sFPR32Op>;
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let Predicates = [HasFPUv2_DF] in
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def _D : F_ACCUM_XYZ<1, sop, op, "d", opnode, sFPR64Op>;
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}
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multiclass FT_CMPXY<bits<6> sop, string op> {
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def _S : F_CMPXY<0, sop, op, "s", sFPR32Op>;
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let Predicates = [HasFPUv2_DF] in
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def _D : F_CMPXY<1, sop, op, "d", sFPR64Op>;
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}
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multiclass FT_CMPZX<bits<6> sop, string op> {
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def _S : F_CMPZX<0, sop, op, "s", sFPR32Op>;
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let Predicates = [HasFPUv2_DF] in
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def _D : F_CMPZX<1, sop, op, "d", sFPR64Op>;
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}
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class F_I8_XY_MEM<bits<7> sop, bits<1> sop_su, dag outs, dag ins, string opcodestr, list<dag> pattern>
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: CSKY32Inst<AddrMode32SDF, 0x3d, outs, ins, opcodestr, pattern> {
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bits<5> rx;
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bits<4> vrz;
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bits<8> imm8;
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let Inst{25} = 0;
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let Inst{24 - 21} = imm8{7 - 4}; //imm4h
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let Inst{20 - 16} = rx; //rx
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let Inst{15 - 9} = sop;
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let Inst{8} = sop_su;
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let Inst{7 - 4} = imm8{3 - 0}; // imm4l
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let Inst{3 - 0} = vrz;
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}
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class F_I4_XY_MEM<bits<7> sop, bits<1> sop_su, dag outs, dag ins, string opcodestr, list<dag> pattern>
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: CSKY32Inst<AddrMode32SDF, 0x3d, outs, ins, opcodestr, pattern> {
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bits<10> regs;
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bits<5> rx;
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let Inst{25} = 0;
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let Inst{24 - 21} = regs{3-0}; //imm4
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let Inst{20 - 16} = rx; //rx
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let Inst{15 - 9} = sop;
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let Inst{8} = sop_su;
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let Inst{7 - 4} = 0;
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let Inst{3 - 0} = regs{8-5};
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}
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class F_I8_Z_MEM<bits<7> sop, bits<1> sop_su, dag outs, dag ins, string opcodestr, list<dag> pattern>
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: CSKY32Inst<AddrModeNone, 0x3d, outs, ins, opcodestr, pattern> {
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bits<4> vrz;
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bits<8> imm8;
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let Inst{25} = 0;
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let Inst{24 - 21} = imm8{7 - 4}; //imm4h
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let Inst{20 - 16} = 0; //rx
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let Inst{15 - 9} = sop;
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let Inst{8} = sop_su;
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let Inst{7 - 4} = imm8{3 - 0}; // imm4l
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let Inst{3 - 0} = vrz;
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}
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class F_XYZ_MEM<bits<7> sop, bits<1> sop_su, dag outs, dag ins, string opcodestr, list<dag> pattern>
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: CSKY32Inst<AddrModeNone, 0x3d, outs, ins, opcodestr, pattern> {
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bits<5> rx;
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bits<5> ry;
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bits<4> vrz;
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bits<2> imm;
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let Inst{25 - 21} = ry; // ry;
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let Inst{20 - 16} = rx; // rx;
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let Inst{15 - 9} = sop;
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let Inst{8} = sop_su;
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let Inst{7} = 0;
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let Inst{6,5} = imm; // shift;
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let Inst{4} = 0;
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let Inst{3 - 0} = vrz;
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}
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class F_XYAI_LD<bits<7> sop, bits<1> sop_su, string op, string op_su,
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RegisterOperand regtype, Operand operand>
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: F_I8_XY_MEM<sop, sop_su, (outs regtype:$vrz), (ins GPR:$rx, operand:$imm8),
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!strconcat(op#op_su, "\t$vrz, ($rx, ${imm8})"), []>;
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class F_XYAR_LD<bits<7> sop, bits<1> sop_su, string op, string op_su,
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RegisterOperand regtype>
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: F_XYZ_MEM<sop, sop_su, (outs regtype:$vrz), (ins GPR:$rx, GPR:$ry, uimm2:$imm),
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op#op_su#"\t$vrz, ($rx, $ry << ${imm})", []>;
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class F_XYAI_ST<bits<7> sop, bits<1> sop_su, string op, string op_su,
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RegisterOperand regtype, Operand operand>
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: F_I8_XY_MEM<sop, sop_su, (outs), (ins regtype:$vrz, GPR:$rx, operand:$imm8),
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!strconcat(op#op_su, "\t$vrz, ($rx, ${imm8})"), []>;
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class F_XYAR_ST<bits<7> sop, bits<1> sop_su, string op, string op_su,
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RegisterOperand regtype>
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: F_XYZ_MEM<sop, sop_su, (outs), (ins regtype:$vrz, GPR:$rx, GPR:$ry, uimm2:$imm),
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op#op_su#"\t$vrz, ($rx, $ry << ${imm})", []>;
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def Mem8SL2 : Operand<iPTR>, ComplexPattern<iPTR, 2, "SelectAddrRegImm8", []> {
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let MIOperandInfo = (ops GPR, i32imm);
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let PrintMethod = "printAddrModeRegImmOperand";
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let EncoderMethod = "getAddrModeFloatImm8_sl2OpValue";
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}
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def FRRS : Operand<iPTR>, ComplexPattern<iPTR, 3, "SelectAddrRegReg", []> {
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let MIOperandInfo = (ops GPR, GPR, i32imm);
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let PrintMethod = "printAddrModeRegRegSLOperand";
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let EncoderMethod = "getAddrModeFloatRegRegSLOpValue";
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}
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multiclass FT_XYAI_LD<bits<7> sop, string op> {
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def _S : F_XYAI_LD<sop, 0, op, "s", sFPR32Op, uimm8_2>;
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let Predicates = [HasFPUv2_DF] in
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def _D : F_XYAI_LD<sop, 1, op, "d", sFPR64Op, uimm8_2>;
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}
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multiclass FT_XYAR_LD<bits<7> sop, string op> {
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def _S : F_XYAR_LD<sop, 0, op, "s", sFPR32Op>;
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let Predicates = [HasFPUv2_DF] in
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def _D : F_XYAR_LD<sop, 1, op, "d", sFPR64Op>;
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}
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multiclass FT_XYAI_ST<bits<7> sop, string op> {
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def _S : F_XYAI_ST<sop, 0, op, "s", sFPR32Op, uimm8_2>;
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let Predicates = [HasFPUv2_DF] in
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def _D : F_XYAI_ST<sop, 1, op, "d", sFPR64Op, uimm8_2>;
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}
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multiclass FT_XYAR_ST<bits<7> sop, string op> {
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def _S : F_XYAR_ST<sop, 0, op, "s", sFPR32Op>;
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let Predicates = [HasFPUv2_DF] in
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def _D : F_XYAR_ST<sop, 1, op, "d", sFPR64Op>;
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}
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multiclass FT_XYAR_STM<bits<7> sop, string op> {
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def _S : F_I4_XY_MEM<sop, 0, (outs),
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(ins GPR:$rx, regseq_f1:$regs, variable_ops),
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!strconcat(op#"s", "\t$regs, (${rx})"), []>;
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let Predicates = [HasFPUv2_DF] in
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def _D : F_I4_XY_MEM<sop, 1, (outs),
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(ins GPR:$rx, regseq_d1:$regs, variable_ops),
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!strconcat(op#"d", "\t$regs, (${rx})"), []>;
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}
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multiclass FT_XYAR_LDM<bits<7> sop, string op> {
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def _S : F_I4_XY_MEM<sop, 0, (outs),
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(ins GPR:$rx, regseq_f1:$regs, variable_ops),
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!strconcat(op#"s", "\t$regs, (${rx})"), []>;
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let Predicates = [HasFPUv2_DF] in
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def _D : F_I4_XY_MEM<sop, 1, (outs),
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(ins GPR:$rx, regseq_d1:$regs, variable_ops),
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!strconcat(op#"d", "\t$regs, (${rx})"), []>;
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}
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