4ad517e6b0
CSKY arch has multiple FPU instruction versions such as FPU, FPUv2 and FPUv3 to implement floating operations. For now, we just only support FPUv2 and FPUv3. It includes the encoding, asm parsing of instructions and codegen of DAG nodes.
209 lines
7.3 KiB
TableGen
209 lines
7.3 KiB
TableGen
//===- CSKYInstrFormatsF2.td - CSKY Float2.0 Instr Format --*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// CSKY Instruction Format Float2.0 Definitions.
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//
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//===----------------------------------------------------------------------===//
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class CSKYInstF2<AddrMode am, dag outs, dag ins, string opcodestr,
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list<dag> pattern>
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: CSKY32Inst<am, 0x3d, outs, ins, opcodestr, pattern> {
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let Predicates = [HasFPUv3_SF];
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let DecoderNamespace = "FPUV3";
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}
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class F2_XYZ<bits<5> datatype, bits<6> sop, string opcodestr, dag outs, dag ins,
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list<dag> pattern>
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: CSKYInstF2<AddrModeNone, outs, ins, opcodestr, pattern> {
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bits<5> vry;
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bits<5> vrx;
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bits<5> vrz;
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let Inst{25-21} = vry;
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let Inst{20-16} = vrx;
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let Inst{15-11} = datatype;
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let Inst{10-5} = sop;
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let Inst{4-0} = vrz;
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}
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multiclass F2_XYZ_T<bits<6> sop, string op, PatFrag opnode> {
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def _S : F2_XYZ<0b00000, sop, op#".32"#"\t$vrz, $vrx, $vry",
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(outs FPR32Op:$vrz), (ins FPR32Op:$vrx, FPR32Op:$vry),
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[(set FPR32Op:$vrz, (opnode FPR32Op:$vrx, FPR32Op:$vry))]>;
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let Predicates = [HasFPUv3_DF] in
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def _D : F2_XYZ<0b00001, sop, op#".64"#"\t$vrz, $vrx, $vry",
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(outs FPR64Op:$vrz), (ins FPR64Op:$vrx, FPR64Op:$vry),
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[(set FPR64Op:$vrz, (opnode FPR64Op:$vrx, FPR64Op:$vry))]>;
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}
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let Constraints = "$vrZ = $vrz" in
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multiclass F2_XYZZ_T<bits<6> sop, string op, PatFrag opnode> {
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def _S : F2_XYZ<0b00000, sop, op#".32"#"\t$vrz, $vrx, $vry",
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(outs FPR32Op:$vrz), (ins FPR32Op:$vrZ, FPR32Op:$vrx, FPR32Op:$vry),
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[(set FPR32Op:$vrz, (opnode FPR32Op:$vrx, FPR32Op:$vry, FPR32Op:$vrZ))]>;
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let Predicates = [HasFPUv3_DF] in
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def _D : F2_XYZ<0b00001, sop, op#".64"#"\t$vrz, $vrx, $vry",
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(outs FPR64Op:$vrz), (ins FPR64Op:$vrZ, FPR64Op:$vrx, FPR64Op:$vry),
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[(set FPR64Op:$vrz, (opnode FPR64Op:$vrx, FPR64Op:$vry, FPR64Op:$vrZ))]>;
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}
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let vry = 0 in {
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class F2_XZ<bits<5> datatype, RegisterOperand regtype, bits<6> sop, string op, SDNode opnode>
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: F2_XYZ<datatype, sop, !strconcat(op, "\t$vrz, $vrx"),
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(outs regtype:$vrz), (ins regtype:$vrx),
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[(set regtype:$vrz, (opnode regtype:$vrx))]>;
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class F2_XZ_SET<bits<5> datatype, RegisterOperand regtype, bits<6> sop, string op>
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: F2_XYZ<datatype, sop, !strconcat(op, "\t$vrz, $vrx"),
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(outs regtype:$vrz), (ins regtype:$vrx),
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[]>;
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class F2_XZ_P<bits<5> datatype, bits<6> sop, string op, list<dag> pattern = [],
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dag outs, dag ins>
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: F2_XYZ<datatype, sop, op#"\t$vrz, $vrx", outs, ins, pattern>;
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}
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multiclass F2_XZ_RM<bits<5> datatype, bits<4> sop, string op, dag outs, dag ins> {
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def _RN : F2_XZ_P<datatype, {sop, 0b00}, op#".rn", [], outs, ins>;
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def _RZ : F2_XZ_P<datatype, {sop, 0b01}, op#".rz", [], outs, ins>;
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def _RPI : F2_XZ_P<datatype, {sop, 0b10}, op#".rpi", [], outs, ins>;
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def _RNI : F2_XZ_P<datatype, {sop, 0b11}, op#".rni", [], outs, ins>;
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}
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multiclass F2_XZ_T<bits<6> sop, string op, SDNode opnode> {
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def _S : F2_XZ<0b00000, FPR32Op, sop, op#".32", opnode>;
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let Predicates = [HasFPUv3_DF] in
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def _D : F2_XZ<0b00001, FPR64Op, sop, op#".64", opnode>;
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}
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multiclass F2_XZ_SET_T<bits<6> sop, string op, string suffix = ""> {
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def _S : F2_XZ_SET<0b00000, FPR32Op, sop, op#".32"#suffix>;
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let Predicates = [HasFPUv3_DF] in
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def _D : F2_XZ_SET<0b00001, FPR64Op, sop, op#".64"#suffix>;
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}
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let vrz = 0, isCompare = 1 in
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class F2_CXY<bits<5> datatype, RegisterOperand regtype, bits<6> sop, string op>
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: F2_XYZ<datatype, sop, !strconcat(op, "\t$vrx, $vry"),
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(outs CARRY:$ca), (ins regtype:$vrx, regtype:$vry),
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[]>;
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multiclass F2_CXY_T<bits<6> sop, string op> {
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def _S : F2_CXY<0b00000, FPR32Op, sop, op#".32">;
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let Predicates = [HasFPUv3_DF] in
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def _D : F2_CXY<0b00001, FPR64Op, sop, op#".64">;
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}
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let vrz = 0, vry = 0, isCompare = 1 in
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class F2_CX<bits<5> datatype, RegisterOperand regtype, bits<6> sop, string op>
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: F2_XYZ<datatype, sop, !strconcat(op, "\t$vrx"),
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(outs CARRY:$ca), (ins regtype:$vrx),
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[]>;
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multiclass F2_CX_T<bits<6> sop, string op> {
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def _S : F2_CX<0b00000, FPR32Op, sop, op#".32">;
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let Predicates = [HasFPUv3_DF] in
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def _D : F2_CX<0b00001, FPR64Op, sop, op#".64">;
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}
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class F2_LDST<bits<2> datatype, bits<1> sop, string op, dag outs, dag ins>
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: CSKYInstF2<AddrMode32SDF, outs, ins,
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!strconcat(op, "\t$vrz, ($rx, ${imm8})"), []> {
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bits<10> imm8;
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bits<5> rx;
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bits<5> vrz;
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let Inst{25} = vrz{4};
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let Inst{24-21} = imm8{7-4};
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let Inst{20-16} = rx;
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let Inst{15-11} = 0b00100;
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let Inst{10} = sop;
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let Inst{9-8} = datatype;
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let Inst{7-4} = imm8{3-0};
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let Inst{3-0} = vrz{3-0};
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}
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class F2_LDST_S<bits<1> sop, string op, dag outs, dag ins>
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: F2_LDST<0b00, sop, op#".32", outs, ins>;
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class F2_LDST_D<bits<1> sop, string op, dag outs, dag ins>
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: F2_LDST<0b01, sop, op#".64", outs, ins>;
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class F2_LDSTM<bits<2> datatype, bits<1> sop, bits<3> sop2, string op, dag outs, dag ins>
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: CSKYInstF2<AddrMode32SDF, outs, ins,
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!strconcat(op, "\t$regs, (${rx})"), []> {
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bits<10> regs;
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bits<5> rx;
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let Inst{25-21} = regs{4-0};
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let Inst{20-16} = rx;
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let Inst{15-11} = 0b00110;
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let Inst{10} = sop;
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let Inst{9-8} = datatype;
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let Inst{7-5} = sop2;
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let Inst{4-0} = regs{9-5};
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}
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class F2_LDSTM_S<bits<1> sop, bits<3> sop2, string op, dag outs, dag ins>
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: F2_LDSTM<0b00, sop, sop2, op#".32", outs, ins>;
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class F2_LDSTM_D<bits<1> sop, bits<3> sop2, string op, dag outs, dag ins>
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: F2_LDSTM<0b01, sop, sop2, op#".64", outs, ins>;
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class F2_LDSTR<bits<2> datatype, bits<1> sop, string op, dag outs, dag ins>
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: CSKYInstF2<AddrModeNone, outs, ins,
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op#"\t$rz, ($rx, $ry << ${imm})", []> {
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bits<5> rx;
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bits<5> ry;
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bits<5> rz;
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bits<2> imm;
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let Inst{25-21} = ry;
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let Inst{20-16} = rx;
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let Inst{15-11} = 0b00101;
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let Inst{10} = sop;
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let Inst{9-8} = datatype;
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let Inst{7} = 0;
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let Inst{6-5} = imm;
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let Inst{4-0} = rz;
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}
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class F2_LDSTR_S<bits<1> sop, string op, dag outs, dag ins>
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: F2_LDSTR<0b00, sop, op#".32", outs, ins>;
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class F2_LDSTR_D<bits<1> sop, string op, dag outs, dag ins>
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: F2_LDSTR<0b01, sop, op#".64", outs, ins>;
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class F2_CXYZ<bits<5> datatype, RegisterOperand regtype, bits<6> sop, string op>
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: F2_XYZ<datatype, sop, !strconcat(op, "\t$vrz, $vrx, $vry"),
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(outs regtype:$vrz), (ins CARRY:$ca, regtype:$vrx, regtype:$vry),
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[]>;
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multiclass F2_CXYZ_T<bits<6> sop, string op> {
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def _S : F2_CXYZ<0b00000, FPR32Op, sop, op#".32">;
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let Predicates = [HasFPUv3_DF] in
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def _D : F2_CXYZ<0b00001, FPR64Op, sop, op#".64">;
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}
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class F2_LRW<bits<2> datatype, bits<1> sop, string op, dag outs, dag ins>
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: CSKYInstF2<AddrModeNone, outs, ins,
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!strconcat(op, "\t$vrz, ${imm8}"), []> {
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bits<10> imm8;
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bits<5> rx;
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bits<5> vrz;
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let Inst{25} = vrz{4};
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let Inst{24-21} = imm8{7-4};
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let Inst{20-16} = 0;
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let Inst{15-11} = 0b00111;
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let Inst{10} = sop;
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let Inst{9-8} = datatype;
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let Inst{7-4} = imm8{3-0};
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let Inst{3-0} = vrz{3-0};
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}
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