a47c35a699
The createSIMachineScheduler & createPostMachineScheduler target hooks are currently placed in the PassConfig interface. Moving it out to TargetMachine so that both legacy and the new pass manager can effectively use them.
91 lines
3.1 KiB
C++
91 lines
3.1 KiB
C++
//===-- PPCTargetMachine.h - Define TargetMachine for PowerPC ---*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the PowerPC specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_POWERPC_PPCTARGETMACHINE_H
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#define LLVM_LIB_TARGET_POWERPC_PPCTARGETMACHINE_H
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#include "PPCInstrInfo.h"
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#include "PPCSubtarget.h"
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#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
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#include "llvm/IR/DataLayout.h"
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#include <optional>
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namespace llvm {
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/// Common code between 32-bit and 64-bit PowerPC targets.
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///
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class PPCTargetMachine final : public CodeGenTargetMachineImpl {
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public:
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enum PPCABI { PPC_ABI_UNKNOWN, PPC_ABI_ELFv1, PPC_ABI_ELFv2 };
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enum Endian { NOT_DETECTED, LITTLE, BIG };
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private:
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std::unique_ptr<TargetLoweringObjectFile> TLOF;
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PPCABI TargetABI;
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Endian Endianness = Endian::NOT_DETECTED;
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mutable bool HasGlibcHWCAPAccess = false;
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mutable StringMap<std::unique_ptr<PPCSubtarget>> SubtargetMap;
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public:
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PPCTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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std::optional<Reloc::Model> RM,
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std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
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bool JIT);
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~PPCTargetMachine() override;
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const PPCSubtarget *getSubtargetImpl(const Function &F) const override;
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// DO NOT IMPLEMENT: There is no such thing as a valid default subtarget,
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// subtargets are per-function entities based on the target-specific
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// attributes of each function.
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const PPCSubtarget *getSubtargetImpl() const = delete;
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// Pass Pipeline Configuration
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TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
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TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
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TargetLoweringObjectFile *getObjFileLowering() const override {
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return TLOF.get();
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}
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MachineFunctionInfo *
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createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
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const TargetSubtargetInfo *STI) const override;
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ScheduleDAGInstrs *
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createMachineScheduler(MachineSchedContext *C) const override;
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ScheduleDAGInstrs *
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createPostMachineScheduler(MachineSchedContext *C) const override;
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bool isELFv2ABI() const { return TargetABI == PPC_ABI_ELFv2; }
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bool hasGlibcHWCAPAccess() const { return HasGlibcHWCAPAccess; }
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void setGlibcHWCAPAccess(bool Val = true) const { HasGlibcHWCAPAccess = Val; }
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bool isPPC64() const {
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const Triple &TT = getTargetTriple();
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return (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le);
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};
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bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
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// Addrspacecasts are always noops.
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return true;
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}
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bool isLittleEndian() const;
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int unqualifiedInlineAsmVariant() const override { return 1; }
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};
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} // end namespace llvm
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#endif
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