3cac26f541
This is the GISel version of #120666. Also supports both unsigned and signed version of min & max.
30 lines
1.0 KiB
TableGen
30 lines
1.0 KiB
TableGen
//=- RISCVCombine.td - Define RISC-V Combine Rules -----------*- tablegen -*-=//
|
|
//
|
|
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
|
// See https://llvm.org/LICENSE.txt for license information.
|
|
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "llvm/Target/GlobalISel/Combine.td"
|
|
|
|
def RISCVPreLegalizerCombiner: GICombiner<
|
|
"RISCVPreLegalizerCombinerImpl", [all_combines]> {
|
|
}
|
|
|
|
def RISCVO0PreLegalizerCombiner: GICombiner<
|
|
"RISCVO0PreLegalizerCombinerImpl", [optnone_combines]> {
|
|
}
|
|
|
|
// Post-legalization combines which are primarily optimizations.
|
|
// TODO: Add more combines.
|
|
def RISCVPostLegalizerCombiner
|
|
: GICombiner<"RISCVPostLegalizerCombinerImpl",
|
|
[sub_to_add, combines_for_extload, redundant_and,
|
|
identity_combines, shift_immed_chain,
|
|
commute_constant_to_rhs, simplify_neg_minmax]> {
|
|
}
|