283f53ac6f
Similar to #139872. This patch adds isel patterns to match `riscv_brcc` and `riscv_selectcc_frag` to XAndesPerf branch instructions.
161 lines
6.3 KiB
TableGen
161 lines
6.3 KiB
TableGen
//===-- RISCVInstrPredicates.td - Instruction Predicates ---*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the RISC-V instruction predicates.
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//
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//===----------------------------------------------------------------------===//
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// This predicate is true when the rs2 operand of vlse or vsse is x0, false
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// otherwise.
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def VLDSX0Pred : MCSchedPredicate<CheckRegOperand<3, X0>>;
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// Returns true if this is the sext.w pattern, addiw rd, rs1, 0.
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def isSEXT_W
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: TIIPredicate<"isSEXT_W",
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MCReturnStatement<CheckAll<[
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CheckOpcode<[ADDIW]>,
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CheckIsRegOperand<1>,
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CheckIsImmOperand<2>,
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CheckImmOperand<2, 0>
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]>>>;
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// Returns true if this is the zext.w pattern, adduw rd, rs1, x0.
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def isZEXT_W
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: TIIPredicate<"isZEXT_W",
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MCReturnStatement<CheckAll<[
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CheckOpcode<[ADD_UW]>,
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CheckIsRegOperand<1>,
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CheckIsRegOperand<2>,
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CheckRegOperand<2, X0>
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]>>>;
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// Returns true if this is the zext.b pattern, andi rd, rs1, 255.
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def isZEXT_B
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: TIIPredicate<"isZEXT_B",
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MCReturnStatement<CheckAll<[
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CheckOpcode<[ANDI]>,
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CheckIsRegOperand<1>,
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CheckIsImmOperand<2>,
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CheckImmOperand<2, 255>
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]>>>;
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def isSelectPseudo
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: TIIPredicate<"isSelectPseudo",
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MCReturnStatement<
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CheckOpcode<[
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Select_GPR_Using_CC_GPR,
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Select_GPR_Using_CC_SImm5_CV,
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Select_GPRNoX0_Using_CC_SImm5NonZero_QC,
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Select_GPRNoX0_Using_CC_UImm5NonZero_QC,
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Select_GPRNoX0_Using_CC_SImm16NonZero_QC,
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Select_GPRNoX0_Using_CC_UImm16NonZero_QC,
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Select_GPR_Using_CC_UImmLog2XLen_NDS,
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Select_GPR_Using_CC_UImm7_NDS,
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Select_FPR16_Using_CC_GPR,
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Select_FPR16INX_Using_CC_GPR,
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Select_FPR32_Using_CC_GPR,
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Select_FPR32INX_Using_CC_GPR,
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Select_FPR64_Using_CC_GPR,
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Select_FPR64INX_Using_CC_GPR,
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Select_FPR64IN32X_Using_CC_GPR
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]>>>;
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// Returns true if this is a vector configuration instruction.
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def isVectorConfigInstr
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: TIIPredicate<"isVectorConfigInstr",
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MCReturnStatement<
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CheckOpcode<[
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PseudoVSETVLI,
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PseudoVSETVLIX0,
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PseudoVSETVLIX0X0,
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PseudoVSETIVLI
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]>>>;
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// Return true if this is 'vsetvli x0, x0, vtype' which preserves
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// VL and only sets VTYPE.
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def isVLPreservingConfig
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: TIIPredicate<"isVLPreservingConfig",
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MCReturnStatement<CheckOpcode<[PseudoVSETVLIX0X0]>>>;
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def isFloatScalarMoveOrScalarSplatInstr
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: TIIPredicate<"isFloatScalarMoveOrScalarSplatInstr",
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MCReturnStatement<
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CheckOpcode<!listflatten([
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!instances<Pseudo>("^PseudoVFMV_S_F.*"),
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!instances<Pseudo>("^PseudoVFMV_V_F.*")
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])>>>;
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def isScalarExtractInstr
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: TIIPredicate<"isScalarExtractInstr",
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MCReturnStatement<
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CheckOpcode<!listflatten([
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!instances<Pseudo>("^PseudoVMV_X_S.*"),
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!instances<Pseudo>("^PseudoVFMV_F.*_S.*")
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])>>>;
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def isVExtractInstr
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: TIIPredicate<"isVExtractInstr",
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MCReturnStatement<
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CheckOpcode<
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!instances<Instruction>("^PseudoRI_VEXTRACT.*")>>>;
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def isScalarInsertInstr
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: TIIPredicate<"isScalarInsertInstr",
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MCReturnStatement<
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CheckOpcode<!listflatten([
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!instances<Pseudo>("^PseudoVMV_S_X.*"),
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!instances<Pseudo>("^PseudoVFMV_S_F.*")
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])>>>;
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def isScalarSplatInstr
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: TIIPredicate<"isScalarSplatInstr",
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MCReturnStatement<
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CheckOpcode<!listflatten([
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!instances<Pseudo>("^PseudoVMV_V_I.*"),
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!instances<Pseudo>("^PseudoVMV_V_X.*"),
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!instances<Pseudo>("^PseudoVFMV_V_F.*")
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])>>>;
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def isVSlideInstr
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: TIIPredicate<"isVSlideInstr",
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MCReturnStatement<
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CheckOpcode<!listflatten([
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!instances<Pseudo>("^PseudoVSLIDEDOWN_VX.*"),
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!instances<Pseudo>("^PseudoVSLIDEDOWN_VI.*"),
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!instances<Pseudo>("^PseudoVSLIDEUP_VX.*"),
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!instances<Pseudo>("^PseudoVSLIDEUP_VI.*")
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])>>>;
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def isFaultOnlyFirstLoad
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: TIIPredicate<"isFaultOnlyFirstLoad",
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MCReturnStatement<
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CheckOpcode<
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!instances<Pseudo>(
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"^PseudoVL(SEG[2-8])?E(8|16|32|64)FF_V.*")>>>;
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def isNonZeroLoadImmediate
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: TIIPredicate<"isNonZeroLoadImmediate",
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MCReturnStatement<CheckAll<[
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CheckOpcode<[ADDI]>,
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CheckIsRegOperand<1>,
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CheckRegOperand<1, X0>,
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CheckIsImmOperand<2>,
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CheckNot<CheckImmOperand<2, 0>>
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]>>>;
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def ignoresVXRM
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: TIIPredicate<"ignoresVXRM",
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MCOpcodeSwitchStatement<
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[MCOpcodeSwitchCase<
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!listflatten([
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!instances<Pseudo>("^PseudoVNCLIP_WI.*"),
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!instances<Pseudo>("^PseudoVNCLIPU_WI.*")
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]),
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MCReturnStatement<CheckImmOperand<3, 0>>>],
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MCReturnStatement<FalsePred>>>;
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