b57df56b48
There will be more schedule definitions for vendor extentions and we need to add these `UnsupportedSchedXXX` to exsiting models every time we add new schedule definitions. The fact is that each vendor will barely implement other vendors' extensions, so we can package these definitions into one.
502 lines
17 KiB
TableGen
502 lines
17 KiB
TableGen
//===-- RISCVSchedGenericOOO.td - Generic OOO Processor ----*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// We assume that:
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// * 6-issue out-of-order CPU with 192 ROB entries.
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// * Units:
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// * IXU (Integer ALU Unit): 4 units, only one can execute mul/div.
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// * FXU (Floating-point Unit): 2 units.
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// * LSU (Load/Store Unit): 2 units.
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// * Latency:
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// * Integer instructions: 1 cycle.
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// * Multiplication instructions: 4 cycles.
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// * Division instructions: 13-21 cycles.
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// * Floating-point instructions: 2-6 cycles.
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// * Floating-point fdiv/fsqrt instructions: 9-21 cycles.
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// * Load/Store:
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// * IXU: 4 cycles.
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// * FXU: 4 cycles.
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// * Integer/floating-point/vector div/rem/sqrt/... are non-pipelined.
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//
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// TODO: Add vector scheduling.
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//===----------------------------------------------------------------------===//
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def GenericOOOModel : SchedMachineModel {
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int IssueWidth = 6;
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int MicroOpBufferSize = 192;
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int LoadLatency = 4;
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int MispredictPenalty = 8;
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let CompleteModel = 0;
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}
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let SchedModel = GenericOOOModel in {
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//===----------------------------------------------------------------------===//
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// Resource groups
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//===----------------------------------------------------------------------===//
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def GenericOOOBranch : ProcResource<1>;
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def GenericOOOMulDiv : ProcResource<1>;
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def GenericOOOInt : ProcResource<2>;
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def GenericOOOALU
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: ProcResGroup<[GenericOOOBranch, GenericOOOMulDiv, GenericOOOInt]>;
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def GenericOOOLSU : ProcResource<2>;
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def GenericOOOFMulDiv : ProcResource<1>;
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def GenericOOOFloat : ProcResource<1>;
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def GenericOOOFPU : ProcResGroup<[GenericOOOFMulDiv, GenericOOOFloat]>;
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//===----------------------------------------------------------------------===//
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// Branches
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//===----------------------------------------------------------------------===//
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def : WriteRes<WriteJmp, [GenericOOOBranch]>;
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def : WriteRes<WriteJalr, [GenericOOOBranch]>;
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def : WriteRes<WriteJal, [GenericOOOBranch]>;
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//===----------------------------------------------------------------------===//
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// Integer arithmetic and logic
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//===----------------------------------------------------------------------===//
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def : WriteRes<WriteIALU, [GenericOOOALU]>;
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def : WriteRes<WriteIALU32, [GenericOOOALU]>;
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def : WriteRes<WriteShiftImm, [GenericOOOALU]>;
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def : WriteRes<WriteShiftImm32, [GenericOOOALU]>;
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def : WriteRes<WriteShiftReg, [GenericOOOALU]>;
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def : WriteRes<WriteShiftReg32, [GenericOOOALU]>;
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//===----------------------------------------------------------------------===//
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// Integer multiplication
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//===----------------------------------------------------------------------===//
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let Latency = 4 in {
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def : WriteRes<WriteIMul, [GenericOOOMulDiv]>;
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def : WriteRes<WriteIMul32, [GenericOOOMulDiv]>;
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}
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//===----------------------------------------------------------------------===//
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// Integer division
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//===----------------------------------------------------------------------===//
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def : WriteRes<WriteIDiv32, [GenericOOOMulDiv]> {
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let Latency = 13;
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let ReleaseAtCycles = [13];
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}
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def : WriteRes<WriteIDiv, [GenericOOOMulDiv]> {
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let Latency = 21;
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let ReleaseAtCycles = [21];
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}
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def : WriteRes<WriteIRem32, [GenericOOOMulDiv]> {
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let Latency = 13;
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let ReleaseAtCycles = [13];
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}
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def : WriteRes<WriteIRem, [GenericOOOMulDiv]> {
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let Latency = 21;
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let ReleaseAtCycles = [21];
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}
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//===----------------------------------------------------------------------===//
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// Integer memory
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//===----------------------------------------------------------------------===//
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// Load
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let Latency = 4 in {
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def : WriteRes<WriteLDB, [GenericOOOLSU]>;
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def : WriteRes<WriteLDH, [GenericOOOLSU]>;
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def : WriteRes<WriteLDW, [GenericOOOLSU]>;
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def : WriteRes<WriteLDD, [GenericOOOLSU]>;
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}
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// Store
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def : WriteRes<WriteSTB, [GenericOOOLSU]>;
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def : WriteRes<WriteSTH, [GenericOOOLSU]>;
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def : WriteRes<WriteSTW, [GenericOOOLSU]>;
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def : WriteRes<WriteSTD, [GenericOOOLSU]>;
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//===----------------------------------------------------------------------===//
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// Atomic
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//===----------------------------------------------------------------------===//
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let Latency = 4 in {
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def : WriteRes<WriteAtomicLDW, [GenericOOOLSU]>;
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def : WriteRes<WriteAtomicLDD, [GenericOOOLSU]>;
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}
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let Latency = 5 in {
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def : WriteRes<WriteAtomicW, [GenericOOOLSU]>;
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def : WriteRes<WriteAtomicD, [GenericOOOLSU]>;
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}
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def : WriteRes<WriteAtomicSTW, [GenericOOOLSU]>;
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def : WriteRes<WriteAtomicSTD, [GenericOOOLSU]>;
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//===----------------------------------------------------------------------===//
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// Floating-point
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//===----------------------------------------------------------------------===//
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// Floating-point load
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let Latency = 4 in {
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def : WriteRes<WriteFLD32, [GenericOOOLSU]>;
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def : WriteRes<WriteFLD64, [GenericOOOLSU]>;
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}
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// Floating-point store
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def : WriteRes<WriteFST32, [GenericOOOLSU]>;
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def : WriteRes<WriteFST64, [GenericOOOLSU]>;
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// Arithmetic and logic
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let Latency = 2 in {
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def : WriteRes<WriteFAdd32, [GenericOOOFPU]>;
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def : WriteRes<WriteFAdd64, [GenericOOOFPU]>;
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}
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def : WriteRes<WriteFSGNJ32, [GenericOOOFPU]>;
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def : WriteRes<WriteFSGNJ64, [GenericOOOFPU]>;
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def : WriteRes<WriteFMinMax32, [GenericOOOFPU]>;
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def : WriteRes<WriteFMinMax64, [GenericOOOFPU]>;
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// Compare
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let Latency = 2 in {
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def : WriteRes<WriteFCmp32, [GenericOOOFPU]>;
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def : WriteRes<WriteFCmp64, [GenericOOOFPU]>;
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}
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// Multiplication
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let Latency = 4 in {
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def : WriteRes<WriteFMul32, [GenericOOOFMulDiv]>;
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def : WriteRes<WriteFMul64, [GenericOOOFMulDiv]>;
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}
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// FMA
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let Latency = 6 in {
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def : WriteRes<WriteFMA32, [GenericOOOFMulDiv]>;
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def : WriteRes<WriteFMA64, [GenericOOOFMulDiv]>;
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}
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// Division
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let Latency = 13, ReleaseAtCycles = [13] in {
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def : WriteRes<WriteFDiv32, [GenericOOOFMulDiv]>;
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def : WriteRes<WriteFSqrt32, [GenericOOOFMulDiv]>;
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}
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let Latency = 17, ReleaseAtCycles = [17] in {
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def : WriteRes<WriteFDiv64, [GenericOOOFMulDiv]>;
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def : WriteRes<WriteFSqrt64, [GenericOOOFMulDiv]>;
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}
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// Conversions
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let Latency = 2 in {
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def : WriteRes<WriteFCvtI32ToF32, [GenericOOOFPU]>;
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def : WriteRes<WriteFCvtI32ToF64, [GenericOOOFPU]>;
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def : WriteRes<WriteFCvtI64ToF32, [GenericOOOFPU]>;
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def : WriteRes<WriteFCvtI64ToF64, [GenericOOOFPU]>;
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}
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let Latency = 2 in {
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def : WriteRes<WriteFCvtF32ToI32, [GenericOOOFPU]>;
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def : WriteRes<WriteFCvtF32ToI64, [GenericOOOFPU]>;
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}
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let Latency = 2 in {
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def : WriteRes<WriteFCvtF64ToI32, [GenericOOOFPU]>;
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def : WriteRes<WriteFCvtF64ToI64, [GenericOOOFPU]>;
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}
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let Latency = 2 in {
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def : WriteRes<WriteFCvtF64ToF32, [GenericOOOFPU]>;
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def : WriteRes<WriteFCvtF32ToF64, [GenericOOOFPU]>;
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}
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let Latency = 2 in {
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def : WriteRes<WriteFMovI32ToF32, [GenericOOOFPU]>;
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def : WriteRes<WriteFMovI64ToF64, [GenericOOOFPU]>;
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def : WriteRes<WriteFMovF32ToI32, [GenericOOOFPU]>;
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def : WriteRes<WriteFMovF64ToI64, [GenericOOOFPU]>;
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}
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// Classify
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def : WriteRes<WriteFClass32, [GenericOOOFPU]>;
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def : WriteRes<WriteFClass64, [GenericOOOFPU]>;
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//===----------------------------------------------------------------------===//
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// Zicsr extension
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//===----------------------------------------------------------------------===//
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def : WriteRes<WriteCSR, [GenericOOOALU]>;
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//===----------------------------------------------------------------------===//
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// Zabha extension
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//===----------------------------------------------------------------------===//
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let Latency = 5 in {
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def : WriteRes<WriteAtomicB, [GenericOOOLSU]>;
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def : WriteRes<WriteAtomicH, [GenericOOOLSU]>;
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}
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//===----------------------------------------------------------------------===//
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// Zba extension
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//===----------------------------------------------------------------------===//
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def : WriteRes<WriteSHXADD, [GenericOOOALU]>;
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def : WriteRes<WriteSHXADD32, [GenericOOOALU]>;
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//===----------------------------------------------------------------------===//
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// Zbb extension
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//===----------------------------------------------------------------------===//
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def : WriteRes<WriteCLZ, [GenericOOOALU]>;
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def : WriteRes<WriteCTZ, [GenericOOOALU]>;
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def : WriteRes<WriteCPOP, [GenericOOOALU]>;
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def : WriteRes<WriteCLZ32, [GenericOOOALU]>;
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def : WriteRes<WriteCTZ32, [GenericOOOALU]>;
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def : WriteRes<WriteCPOP32, [GenericOOOALU]>;
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def : WriteRes<WriteRotateReg, [GenericOOOALU]>;
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def : WriteRes<WriteRotateImm, [GenericOOOALU]>;
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def : WriteRes<WriteRotateReg32, [GenericOOOALU]>;
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def : WriteRes<WriteRotateImm32, [GenericOOOALU]>;
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def : WriteRes<WriteREV8, [GenericOOOALU]>;
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def : WriteRes<WriteORCB, [GenericOOOALU]>;
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def : WriteRes<WriteIMinMax, [GenericOOOALU]>;
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//===----------------------------------------------------------------------===//
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// Zbc extension
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//===----------------------------------------------------------------------===//
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def : WriteRes<WriteCLMUL, [GenericOOOALU]>;
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//===----------------------------------------------------------------------===//
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// Zbs extension
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//===----------------------------------------------------------------------===//
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def : WriteRes<WriteSingleBit, [GenericOOOALU]>;
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def : WriteRes<WriteSingleBitImm, [GenericOOOALU]>;
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def : WriteRes<WriteBEXT, [GenericOOOALU]>;
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def : WriteRes<WriteBEXTI, [GenericOOOALU]>;
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//===----------------------------------------------------------------------===//
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// Zbkb extension
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//===----------------------------------------------------------------------===//
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def : WriteRes<WriteBREV8, [GenericOOOALU]>;
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def : WriteRes<WritePACK, [GenericOOOALU]>;
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def : WriteRes<WritePACK32, [GenericOOOALU]>;
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def : WriteRes<WriteZIP, [GenericOOOALU]>;
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//===----------------------------------------------------------------------===//
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// Zbkx extension
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//===----------------------------------------------------------------------===//
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def : WriteRes<WriteXPERM, [GenericOOOALU]>;
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//===----------------------------------------------------------------------===//
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// Zfa extension
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//===----------------------------------------------------------------------===//
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let Latency = 2 in {
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def : WriteRes<WriteFRoundF16, [GenericOOOFPU]>;
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def : WriteRes<WriteFRoundF32, [GenericOOOFPU]>;
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def : WriteRes<WriteFRoundF64, [GenericOOOFPU]>;
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}
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let Latency = 2 in {
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def : WriteRes<WriteFLI16, [GenericOOOFPU]>;
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def : WriteRes<WriteFLI32, [GenericOOOFPU]>;
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def : WriteRes<WriteFLI64, [GenericOOOFPU]>;
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}
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//===----------------------------------------------------------------------===//
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// Zfh extension
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//===----------------------------------------------------------------------===//
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// Zfhmin
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// Load/Store
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let Latency = 4 in
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def : WriteRes<WriteFLD16, [GenericOOOLSU]>;
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def : WriteRes<WriteFST16, [GenericOOOLSU]>;
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// Conversions
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let Latency = 2 in {
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def : WriteRes<WriteFCvtF16ToF64, [GenericOOOFPU]>;
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def : WriteRes<WriteFCvtF64ToF16, [GenericOOOFPU]>;
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def : WriteRes<WriteFCvtF32ToF16, [GenericOOOFPU]>;
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def : WriteRes<WriteFCvtF16ToF32, [GenericOOOFPU]>;
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}
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let Latency = 2 in {
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def : WriteRes<WriteFMovI16ToF16, [GenericOOOFPU]>;
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def : WriteRes<WriteFMovF16ToI16, [GenericOOOFPU]>;
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}
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// Other than Zfhmin
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let Latency = 2 in {
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def : WriteRes<WriteFCvtI64ToF16, [GenericOOOFPU]>;
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def : WriteRes<WriteFCvtI32ToF16, [GenericOOOFPU]>;
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def : WriteRes<WriteFCvtF16ToI64, [GenericOOOFPU]>;
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def : WriteRes<WriteFCvtF16ToI32, [GenericOOOFPU]>;
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}
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// Arithmetic and logic
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let Latency = 2 in
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def : WriteRes<WriteFAdd16, [GenericOOOFPU]>;
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def : WriteRes<WriteFSGNJ16, [GenericOOOFPU]>;
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def : WriteRes<WriteFMinMax16, [GenericOOOFPU]>;
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// Compare
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let Latency = 2 in
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def : WriteRes<WriteFCmp16, [GenericOOOFPU]>;
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// Multiplication
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let Latency = 4 in
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def : WriteRes<WriteFMul16, [GenericOOOFMulDiv]>;
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// FMA
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let Latency = 6 in
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def : WriteRes<WriteFMA16, [GenericOOOFMulDiv]>;
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// Division
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let Latency = 9, ReleaseAtCycles = [9] in {
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def : WriteRes<WriteFDiv16, [GenericOOOFMulDiv]>;
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def : WriteRes<WriteFSqrt16, [GenericOOOFMulDiv]>;
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}
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// Classify
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def : WriteRes<WriteFClass16, [GenericOOOFPU]>;
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//===----------------------------------------------------------------------===//
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// Misc
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//===----------------------------------------------------------------------===//
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let Latency = 0 in
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def : WriteRes<WriteNop, [GenericOOOALU]>;
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//===----------------------------------------------------------------------===//
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// Bypass and advance
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//===----------------------------------------------------------------------===//
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def : ReadAdvance<ReadJmp, 0>;
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def : ReadAdvance<ReadJalr, 0>;
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def : ReadAdvance<ReadCSR, 0>;
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def : ReadAdvance<ReadStoreData, 0>;
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def : ReadAdvance<ReadMemBase, 0>;
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def : ReadAdvance<ReadIALU, 0>;
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def : ReadAdvance<ReadIALU32, 0>;
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def : ReadAdvance<ReadShiftImm, 0>;
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def : ReadAdvance<ReadShiftImm32, 0>;
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def : ReadAdvance<ReadShiftReg, 0>;
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def : ReadAdvance<ReadShiftReg32, 0>;
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def : ReadAdvance<ReadIDiv, 0>;
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def : ReadAdvance<ReadIDiv32, 0>;
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def : ReadAdvance<ReadIRem, 0>;
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def : ReadAdvance<ReadIRem32, 0>;
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def : ReadAdvance<ReadIMul, 0>;
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def : ReadAdvance<ReadIMul32, 0>;
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def : ReadAdvance<ReadAtomicWA, 0>;
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def : ReadAdvance<ReadAtomicWD, 0>;
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def : ReadAdvance<ReadAtomicDA, 0>;
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def : ReadAdvance<ReadAtomicDD, 0>;
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def : ReadAdvance<ReadAtomicLDW, 0>;
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def : ReadAdvance<ReadAtomicLDD, 0>;
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def : ReadAdvance<ReadAtomicSTW, 0>;
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def : ReadAdvance<ReadAtomicSTD, 0>;
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def : ReadAdvance<ReadFStoreData, 0>;
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def : ReadAdvance<ReadFMemBase, 0>;
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def : ReadAdvance<ReadFAdd32, 0>;
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def : ReadAdvance<ReadFAdd64, 0>;
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def : ReadAdvance<ReadFMul32, 0>;
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def : ReadAdvance<ReadFMA32, 0>;
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def : ReadAdvance<ReadFMA32Addend, 0>;
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def : ReadAdvance<ReadFMul64, 0>;
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def : ReadAdvance<ReadFMA64, 0>;
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def : ReadAdvance<ReadFMA64Addend, 0>;
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def : ReadAdvance<ReadFDiv32, 0>;
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def : ReadAdvance<ReadFDiv64, 0>;
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def : ReadAdvance<ReadFSqrt32, 0>;
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def : ReadAdvance<ReadFSqrt64, 0>;
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def : ReadAdvance<ReadFCmp32, 0>;
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def : ReadAdvance<ReadFCmp64, 0>;
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def : ReadAdvance<ReadFSGNJ32, 0>;
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def : ReadAdvance<ReadFSGNJ64, 0>;
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def : ReadAdvance<ReadFMinMax32, 0>;
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def : ReadAdvance<ReadFMinMax64, 0>;
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def : ReadAdvance<ReadFCvtF32ToI32, 0>;
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def : ReadAdvance<ReadFCvtF32ToI64, 0>;
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def : ReadAdvance<ReadFCvtF64ToI32, 0>;
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def : ReadAdvance<ReadFCvtF64ToI64, 0>;
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def : ReadAdvance<ReadFCvtI32ToF32, 0>;
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def : ReadAdvance<ReadFCvtI32ToF64, 0>;
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def : ReadAdvance<ReadFCvtI64ToF32, 0>;
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def : ReadAdvance<ReadFCvtI64ToF64, 0>;
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def : ReadAdvance<ReadFCvtF32ToF64, 0>;
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def : ReadAdvance<ReadFCvtF64ToF32, 0>;
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def : ReadAdvance<ReadFMovF32ToI32, 0>;
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def : ReadAdvance<ReadFMovI32ToF32, 0>;
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def : ReadAdvance<ReadFMovF64ToI64, 0>;
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def : ReadAdvance<ReadFMovI64ToF64, 0>;
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def : ReadAdvance<ReadFClass32, 0>;
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def : ReadAdvance<ReadFClass64, 0>;
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// Zabha
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def : ReadAdvance<ReadAtomicBA, 0>;
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def : ReadAdvance<ReadAtomicBD, 0>;
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def : ReadAdvance<ReadAtomicHA, 0>;
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def : ReadAdvance<ReadAtomicHD, 0>;
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// Zba extension
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def : ReadAdvance<ReadSHXADD, 0>;
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def : ReadAdvance<ReadSHXADD32, 0>;
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// Zbb extension
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def : ReadAdvance<ReadRotateImm, 0>;
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def : ReadAdvance<ReadRotateImm32, 0>;
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def : ReadAdvance<ReadRotateReg, 0>;
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def : ReadAdvance<ReadRotateReg32, 0>;
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def : ReadAdvance<ReadCLZ, 0>;
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def : ReadAdvance<ReadCLZ32, 0>;
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def : ReadAdvance<ReadCTZ, 0>;
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def : ReadAdvance<ReadCTZ32, 0>;
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def : ReadAdvance<ReadCPOP, 0>;
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def : ReadAdvance<ReadCPOP32, 0>;
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def : ReadAdvance<ReadREV8, 0>;
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def : ReadAdvance<ReadORCB, 0>;
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def : ReadAdvance<ReadIMinMax, 0>;
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// Zbc extension
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def : ReadAdvance<ReadCLMUL, 0>;
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// Zbs extension
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def : ReadAdvance<ReadSingleBit, 0>;
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def : ReadAdvance<ReadSingleBitImm, 0>;
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// Zbkb
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def : ReadAdvance<ReadBREV8, 0>;
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def : ReadAdvance<ReadPACK, 0>;
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def : ReadAdvance<ReadPACK32, 0>;
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def : ReadAdvance<ReadZIP, 0>;
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|
|
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// Zbkx
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def : ReadAdvance<ReadXPERM, 0>;
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|
|
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// Zfa extension
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def : ReadAdvance<ReadFRoundF32, 0>;
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def : ReadAdvance<ReadFRoundF64, 0>;
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def : ReadAdvance<ReadFRoundF16, 0>;
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|
|
|
// Zfh extension
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def : ReadAdvance<ReadFCvtF16ToF64, 0>;
|
|
def : ReadAdvance<ReadFCvtF64ToF16, 0>;
|
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def : ReadAdvance<ReadFCvtF32ToF16, 0>;
|
|
def : ReadAdvance<ReadFCvtF16ToF32, 0>;
|
|
def : ReadAdvance<ReadFMovI16ToF16, 0>;
|
|
def : ReadAdvance<ReadFMovF16ToI16, 0>;
|
|
|
|
def : ReadAdvance<ReadFAdd16, 0>;
|
|
def : ReadAdvance<ReadFClass16, 0>;
|
|
def : ReadAdvance<ReadFCvtI64ToF16, 0>;
|
|
def : ReadAdvance<ReadFCvtI32ToF16, 0>;
|
|
def : ReadAdvance<ReadFCvtF16ToI64, 0>;
|
|
def : ReadAdvance<ReadFCvtF16ToI32, 0>;
|
|
def : ReadAdvance<ReadFDiv16, 0>;
|
|
def : ReadAdvance<ReadFCmp16, 0>;
|
|
def : ReadAdvance<ReadFMA16, 0>;
|
|
def : ReadAdvance<ReadFMA16Addend, 0>;
|
|
def : ReadAdvance<ReadFMinMax16, 0>;
|
|
def : ReadAdvance<ReadFMul16, 0>;
|
|
def : ReadAdvance<ReadFSGNJ16, 0>;
|
|
def : ReadAdvance<ReadFSqrt16, 0>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Unsupported extensions
|
|
//===----------------------------------------------------------------------===//
|
|
defm : UnsupportedSchedQ;
|
|
defm : UnsupportedSchedV;
|
|
defm : UnsupportedSchedZfaWithQ;
|
|
defm : UnsupportedSchedZvk;
|
|
defm : UnsupportedSchedSFB;
|
|
defm : UnsupportedSchedXsf;
|
|
}
|