b57df56b48
There will be more schedule definitions for vendor extentions and we need to add these `UnsupportedSchedXXX` to exsiting models every time we add new schedule definitions. The fact is that each vendor will barely implement other vendors' extensions, so we can package these definitions into one.
268 lines
9.0 KiB
TableGen
268 lines
9.0 KiB
TableGen
//==- RISCVSchedRocket.td - Rocket Scheduling Definitions ----*- tablegen -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// ===---------------------------------------------------------------------===//
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// The following definitions describe the simpler per-operand machine model.
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// This works with MachineScheduler. See MCSchedule.h for details.
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// Rocket machine model for scheduling and other instruction cost heuristics.
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def RocketModel : SchedMachineModel {
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let MicroOpBufferSize = 0; // Rocket is in-order.
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let IssueWidth = 1; // 1 micro-op is dispatched per cycle.
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let LoadLatency = 3;
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let MispredictPenalty = 3;
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let CompleteModel = false;
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let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,
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HasStdExtZcmt, HasStdExtZknd, HasStdExtZkne,
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HasStdExtZknh, HasStdExtZksed, HasStdExtZksh,
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HasStdExtZkr, HasVInstructions, HasVInstructionsI64];
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}
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//===----------------------------------------------------------------------===//
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// Define each kind of processor resource and number available.
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// Modeling each pipeline as a ProcResource using the BufferSize = 0 since
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// Rocket is in-order.
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let BufferSize = 0 in {
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def RocketUnitALU : ProcResource<1>; // Int ALU
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def RocketUnitIMul : ProcResource<1>; // Int Multiply
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def RocketUnitMem : ProcResource<1>; // Load/Store
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def RocketUnitB : ProcResource<1>; // Branch
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def RocketUnitFPALU : ProcResource<1>; // FP ALU
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}
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let BufferSize = 1 in {
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def RocketUnitIDiv : ProcResource<1>; // Int Division
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def RocketUnitFPDivSqrt : ProcResource<1>; // FP Divide/Sqrt
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}
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//===----------------------------------------------------------------------===//
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let SchedModel = RocketModel in {
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// Branching
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def : WriteRes<WriteJmp, [RocketUnitB]>;
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def : WriteRes<WriteJal, [RocketUnitB]>;
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def : WriteRes<WriteJalr, [RocketUnitB]>;
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// Integer arithmetic and logic
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def : WriteRes<WriteIALU32, [RocketUnitALU]>;
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def : WriteRes<WriteIALU, [RocketUnitALU]>;
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def : WriteRes<WriteShiftImm32, [RocketUnitALU]>;
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def : WriteRes<WriteShiftImm, [RocketUnitALU]>;
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def : WriteRes<WriteShiftReg32, [RocketUnitALU]>;
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def : WriteRes<WriteShiftReg, [RocketUnitALU]>;
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// Integer multiplication
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let Latency = 4 in {
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def : WriteRes<WriteIMul, [RocketUnitIMul]>;
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def : WriteRes<WriteIMul32, [RocketUnitIMul]>;
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}
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// Integer division
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// Worst case latency is used.
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def : WriteRes<WriteIDiv32, [RocketUnitIDiv]> {
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let Latency = 34;
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let ReleaseAtCycles = [34];
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}
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def : WriteRes<WriteIDiv, [RocketUnitIDiv]> {
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let Latency = 33;
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let ReleaseAtCycles = [33];
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}
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// Integer remainder
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def : WriteRes<WriteIRem32, [RocketUnitIDiv]> {
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let Latency = 34;
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let ReleaseAtCycles = [34];
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}
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def : WriteRes<WriteIRem, [RocketUnitIDiv]> {
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let Latency = 33;
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let ReleaseAtCycles = [33];
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}
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// Memory
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def : WriteRes<WriteSTB, [RocketUnitMem]>;
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def : WriteRes<WriteSTH, [RocketUnitMem]>;
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def : WriteRes<WriteSTW, [RocketUnitMem]>;
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def : WriteRes<WriteSTD, [RocketUnitMem]>;
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def : WriteRes<WriteFST32, [RocketUnitMem]>;
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def : WriteRes<WriteFST64, [RocketUnitMem]>;
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let Latency = 3 in {
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def : WriteRes<WriteLDB, [RocketUnitMem]>;
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def : WriteRes<WriteLDH, [RocketUnitMem]>;
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}
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let Latency = 2 in {
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def : WriteRes<WriteLDW, [RocketUnitMem]>;
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def : WriteRes<WriteLDD, [RocketUnitMem]>;
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def : WriteRes<WriteFLD32, [RocketUnitMem]>;
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def : WriteRes<WriteFLD64, [RocketUnitMem]>;
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// Atomic memory
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def : WriteRes<WriteAtomicW, [RocketUnitMem]>;
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def : WriteRes<WriteAtomicD, [RocketUnitMem]>;
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def : WriteRes<WriteAtomicLDW, [RocketUnitMem]>;
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def : WriteRes<WriteAtomicLDD, [RocketUnitMem]>;
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}
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def : WriteRes<WriteAtomicSTW, [RocketUnitMem]>;
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def : WriteRes<WriteAtomicSTD, [RocketUnitMem]>;
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// Single precision.
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let Latency = 4 in {
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def : WriteRes<WriteFAdd32, [RocketUnitFPALU]>;
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def : WriteRes<WriteFSGNJ32, [RocketUnitFPALU]>;
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def : WriteRes<WriteFMinMax32, [RocketUnitFPALU]>;
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}
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// Double precision
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let Latency = 6 in {
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def : WriteRes<WriteFAdd64, [RocketUnitFPALU]>;
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def : WriteRes<WriteFSGNJ64, [RocketUnitFPALU]>;
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def : WriteRes<WriteFMinMax64, [RocketUnitFPALU]>;
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}
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// Conversions
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let Latency = 2 in {
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def : WriteRes<WriteFCvtI32ToF32, [RocketUnitFPALU]>;
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def : WriteRes<WriteFCvtI32ToF64, [RocketUnitFPALU]>;
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def : WriteRes<WriteFCvtI64ToF32, [RocketUnitFPALU]>;
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def : WriteRes<WriteFCvtI64ToF64, [RocketUnitFPALU]>;
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def : WriteRes<WriteFCvtF32ToI32, [RocketUnitFPALU]>;
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def : WriteRes<WriteFCvtF32ToI64, [RocketUnitFPALU]>;
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def : WriteRes<WriteFCvtF64ToI32, [RocketUnitFPALU]>;
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def : WriteRes<WriteFCvtF64ToI64, [RocketUnitFPALU]>;
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def : WriteRes<WriteFCvtF32ToF64, [RocketUnitFPALU]>;
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def : WriteRes<WriteFCvtF64ToF32, [RocketUnitFPALU]>;
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def : WriteRes<WriteFClass32, [RocketUnitFPALU]>;
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def : WriteRes<WriteFClass64, [RocketUnitFPALU]>;
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def : WriteRes<WriteFCmp32, [RocketUnitFPALU]>;
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def : WriteRes<WriteFCmp64, [RocketUnitFPALU]>;
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def : WriteRes<WriteFMovF32ToI32, [RocketUnitFPALU]>;
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def : WriteRes<WriteFMovI32ToF32, [RocketUnitFPALU]>;
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def : WriteRes<WriteFMovF64ToI64, [RocketUnitFPALU]>;
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def : WriteRes<WriteFMovI64ToF64, [RocketUnitFPALU]>;
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}
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// FP multiplication
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let Latency = 5 in {
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def : WriteRes<WriteFMul32, [RocketUnitFPALU]>;
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def : WriteRes<WriteFMA32, [RocketUnitFPALU]>;
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}
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let Latency = 7 in {
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def : WriteRes<WriteFMul64, [RocketUnitFPALU]>;
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def : WriteRes<WriteFMA64, [RocketUnitFPALU]>;
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}
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// FP division
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// FP division unit on Rocket is not pipelined, so set resource cycles to latency.
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let Latency = 20, ReleaseAtCycles = [20] in {
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def : WriteRes<WriteFDiv32, [RocketUnitFPDivSqrt]>;
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def : WriteRes<WriteFDiv64, [RocketUnitFPDivSqrt]>;
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}
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// FP square root unit on Rocket is not pipelined, so set resource cycles to latency.
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def : WriteRes<WriteFSqrt32, [RocketUnitFPDivSqrt]> { let Latency = 20;
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let ReleaseAtCycles = [20]; }
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def : WriteRes<WriteFSqrt64, [RocketUnitFPDivSqrt]> { let Latency = 25;
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let ReleaseAtCycles = [25]; }
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// Others
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def : WriteRes<WriteCSR, []>;
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def : WriteRes<WriteNop, []>;
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def : InstRW<[WriteIALU], (instrs COPY)>;
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//===----------------------------------------------------------------------===//
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// Bypass and advance
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def : ReadAdvance<ReadJmp, 0>;
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def : ReadAdvance<ReadJalr, 0>;
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def : ReadAdvance<ReadCSR, 0>;
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def : ReadAdvance<ReadStoreData, 0>;
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def : ReadAdvance<ReadMemBase, 0>;
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def : ReadAdvance<ReadIALU, 0>;
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def : ReadAdvance<ReadIALU32, 0>;
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def : ReadAdvance<ReadShiftImm, 0>;
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def : ReadAdvance<ReadShiftImm32, 0>;
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def : ReadAdvance<ReadShiftReg, 0>;
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def : ReadAdvance<ReadShiftReg32, 0>;
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def : ReadAdvance<ReadIDiv, 0>;
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def : ReadAdvance<ReadIDiv32, 0>;
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def : ReadAdvance<ReadIRem, 0>;
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def : ReadAdvance<ReadIRem32, 0>;
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def : ReadAdvance<ReadIMul, 0>;
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def : ReadAdvance<ReadIMul32, 0>;
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def : ReadAdvance<ReadAtomicWA, 0>;
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def : ReadAdvance<ReadAtomicWD, 0>;
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def : ReadAdvance<ReadAtomicDA, 0>;
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def : ReadAdvance<ReadAtomicDD, 0>;
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def : ReadAdvance<ReadAtomicLDW, 0>;
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def : ReadAdvance<ReadAtomicLDD, 0>;
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def : ReadAdvance<ReadAtomicSTW, 0>;
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def : ReadAdvance<ReadAtomicSTD, 0>;
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def : ReadAdvance<ReadFStoreData, 0>;
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def : ReadAdvance<ReadFMemBase, 0>;
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def : ReadAdvance<ReadFAdd32, 0>;
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def : ReadAdvance<ReadFAdd64, 0>;
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def : ReadAdvance<ReadFMul32, 0>;
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def : ReadAdvance<ReadFMul64, 0>;
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def : ReadAdvance<ReadFMA32, 0>;
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def : ReadAdvance<ReadFMA32Addend, 0>;
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def : ReadAdvance<ReadFMA64, 0>;
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def : ReadAdvance<ReadFMA64Addend, 0>;
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def : ReadAdvance<ReadFDiv32, 0>;
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def : ReadAdvance<ReadFDiv64, 0>;
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def : ReadAdvance<ReadFSqrt32, 0>;
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def : ReadAdvance<ReadFSqrt64, 0>;
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def : ReadAdvance<ReadFCmp32, 0>;
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def : ReadAdvance<ReadFCmp64, 0>;
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def : ReadAdvance<ReadFSGNJ32, 0>;
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def : ReadAdvance<ReadFSGNJ64, 0>;
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def : ReadAdvance<ReadFMinMax32, 0>;
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def : ReadAdvance<ReadFMinMax64, 0>;
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def : ReadAdvance<ReadFCvtF32ToI32, 0>;
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def : ReadAdvance<ReadFCvtF32ToI64, 0>;
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def : ReadAdvance<ReadFCvtF64ToI32, 0>;
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def : ReadAdvance<ReadFCvtF64ToI64, 0>;
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def : ReadAdvance<ReadFCvtI32ToF32, 0>;
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def : ReadAdvance<ReadFCvtI32ToF64, 0>;
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def : ReadAdvance<ReadFCvtI64ToF32, 0>;
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def : ReadAdvance<ReadFCvtI64ToF64, 0>;
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def : ReadAdvance<ReadFCvtF32ToF64, 0>;
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def : ReadAdvance<ReadFCvtF64ToF32, 0>;
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def : ReadAdvance<ReadFMovF32ToI32, 0>;
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def : ReadAdvance<ReadFMovI32ToF32, 0>;
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def : ReadAdvance<ReadFMovF64ToI64, 0>;
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def : ReadAdvance<ReadFMovI64ToF64, 0>;
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def : ReadAdvance<ReadFClass32, 0>;
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def : ReadAdvance<ReadFClass64, 0>;
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//===----------------------------------------------------------------------===//
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// Unsupported extensions
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defm : UnsupportedSchedQ;
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defm : UnsupportedSchedV;
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defm : UnsupportedSchedZabha;
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defm : UnsupportedSchedZba;
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defm : UnsupportedSchedZbb;
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defm : UnsupportedSchedZbc;
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defm : UnsupportedSchedZbs;
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defm : UnsupportedSchedZbkb;
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defm : UnsupportedSchedZbkx;
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defm : UnsupportedSchedZfa;
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defm : UnsupportedSchedZfhmin;
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defm : UnsupportedSchedSFB;
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defm : UnsupportedSchedZvk;
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defm : UnsupportedSchedXsf;
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}
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