89fd7b3d1e
These are identified by misc-include-cleaner. I've filtered out those that break builds. Also, I'm staying away from llvm-config.h, config.h, and Compiler.h, which likely cause platform- or compiler-specific build failures.
288 lines
10 KiB
C++
288 lines
10 KiB
C++
//===-- SPIRVInstrInfo.cpp - SPIR-V Instruction Information ------*- C++-*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the SPIR-V implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "SPIRVInstrInfo.h"
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#include "SPIRV.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/IR/DebugLoc.h"
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#define GET_INSTRINFO_CTOR_DTOR
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#include "SPIRVGenInstrInfo.inc"
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using namespace llvm;
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SPIRVInstrInfo::SPIRVInstrInfo() : SPIRVGenInstrInfo() {}
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bool SPIRVInstrInfo::isConstantInstr(const MachineInstr &MI) const {
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switch (MI.getOpcode()) {
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case SPIRV::OpConstantTrue:
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case SPIRV::OpConstantFalse:
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case SPIRV::OpConstantI:
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case SPIRV::OpConstantF:
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case SPIRV::OpConstantComposite:
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case SPIRV::OpConstantCompositeContinuedINTEL:
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case SPIRV::OpConstantSampler:
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case SPIRV::OpConstantNull:
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case SPIRV::OpSpecConstantTrue:
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case SPIRV::OpSpecConstantFalse:
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case SPIRV::OpSpecConstant:
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case SPIRV::OpSpecConstantComposite:
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case SPIRV::OpSpecConstantCompositeContinuedINTEL:
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case SPIRV::OpSpecConstantOp:
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case SPIRV::OpUndef:
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case SPIRV::OpConstantFunctionPointerINTEL:
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return true;
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default:
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return false;
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}
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}
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bool SPIRVInstrInfo::isSpecConstantInstr(const MachineInstr &MI) const {
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switch (MI.getOpcode()) {
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case SPIRV::OpSpecConstantTrue:
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case SPIRV::OpSpecConstantFalse:
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case SPIRV::OpSpecConstant:
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case SPIRV::OpSpecConstantComposite:
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case SPIRV::OpSpecConstantCompositeContinuedINTEL:
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case SPIRV::OpSpecConstantOp:
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return true;
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default:
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return false;
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}
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}
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bool SPIRVInstrInfo::isInlineAsmDefInstr(const MachineInstr &MI) const {
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switch (MI.getOpcode()) {
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case SPIRV::OpAsmTargetINTEL:
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case SPIRV::OpAsmINTEL:
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return true;
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default:
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return false;
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}
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}
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bool SPIRVInstrInfo::isTypeDeclInstr(const MachineInstr &MI) const {
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auto &MRI = MI.getMF()->getRegInfo();
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if (MI.getNumDefs() >= 1 && MI.getOperand(0).isReg()) {
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auto DefRegClass = MRI.getRegClassOrNull(MI.getOperand(0).getReg());
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return DefRegClass && DefRegClass->getID() == SPIRV::TYPERegClass.getID();
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} else {
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return MI.getOpcode() == SPIRV::OpTypeForwardPointer ||
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MI.getOpcode() == SPIRV::OpTypeStructContinuedINTEL;
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}
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}
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bool SPIRVInstrInfo::isDecorationInstr(const MachineInstr &MI) const {
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switch (MI.getOpcode()) {
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case SPIRV::OpDecorate:
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case SPIRV::OpDecorateId:
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case SPIRV::OpDecorateString:
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case SPIRV::OpMemberDecorate:
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case SPIRV::OpMemberDecorateString:
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return true;
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default:
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return false;
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}
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}
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bool SPIRVInstrInfo::isAliasingInstr(const MachineInstr &MI) const {
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switch (MI.getOpcode()) {
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case SPIRV::OpAliasDomainDeclINTEL:
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case SPIRV::OpAliasScopeDeclINTEL:
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case SPIRV::OpAliasScopeListDeclINTEL:
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return true;
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default:
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return false;
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}
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}
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bool SPIRVInstrInfo::isHeaderInstr(const MachineInstr &MI) const {
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switch (MI.getOpcode()) {
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case SPIRV::OpCapability:
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case SPIRV::OpExtension:
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case SPIRV::OpExtInstImport:
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case SPIRV::OpMemoryModel:
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case SPIRV::OpEntryPoint:
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case SPIRV::OpExecutionMode:
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case SPIRV::OpExecutionModeId:
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case SPIRV::OpString:
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case SPIRV::OpSourceExtension:
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case SPIRV::OpSource:
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case SPIRV::OpSourceContinued:
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case SPIRV::OpName:
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case SPIRV::OpMemberName:
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case SPIRV::OpModuleProcessed:
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return true;
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default:
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return isTypeDeclInstr(MI) || isConstantInstr(MI) ||
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isDecorationInstr(MI) || isAliasingInstr(MI);
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}
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}
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bool SPIRVInstrInfo::canUseFastMathFlags(const MachineInstr &MI) const {
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switch (MI.getOpcode()) {
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case SPIRV::OpFAddS:
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case SPIRV::OpFSubS:
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case SPIRV::OpFMulS:
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case SPIRV::OpFDivS:
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case SPIRV::OpFRemS:
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case SPIRV::OpFAddV:
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case SPIRV::OpFSubV:
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case SPIRV::OpFMulV:
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case SPIRV::OpFDivV:
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case SPIRV::OpFRemV:
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case SPIRV::OpFMod:
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return true;
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default:
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return false;
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}
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}
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bool SPIRVInstrInfo::canUseNSW(const MachineInstr &MI) const {
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switch (MI.getOpcode()) {
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case SPIRV::OpIAddS:
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case SPIRV::OpIAddV:
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case SPIRV::OpISubS:
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case SPIRV::OpISubV:
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case SPIRV::OpIMulS:
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case SPIRV::OpIMulV:
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case SPIRV::OpShiftLeftLogicalS:
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case SPIRV::OpShiftLeftLogicalV:
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case SPIRV::OpSNegate:
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return true;
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default:
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return false;
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}
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}
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bool SPIRVInstrInfo::canUseNUW(const MachineInstr &MI) const {
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switch (MI.getOpcode()) {
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case SPIRV::OpIAddS:
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case SPIRV::OpIAddV:
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case SPIRV::OpISubS:
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case SPIRV::OpISubV:
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case SPIRV::OpIMulS:
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case SPIRV::OpIMulV:
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return true;
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default:
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return false;
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}
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}
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// Analyze the branching code at the end of MBB, returning
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// true if it cannot be understood (e.g. it's a switch dispatch or isn't
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// implemented for a target). Upon success, this returns false and returns
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// with the following information in various cases:
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//
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// 1. If this block ends with no branches (it just falls through to its succ)
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// just return false, leaving TBB/FBB null.
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// 2. If this block ends with only an unconditional branch, it sets TBB to be
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// the destination block.
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// 3. If this block ends with a conditional branch and it falls through to a
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// successor block, it sets TBB to be the branch destination block and a
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// list of operands that evaluate the condition. These operands can be
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// passed to other TargetInstrInfo methods to create new branches.
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// 4. If this block ends with a conditional branch followed by an
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// unconditional branch, it returns the 'true' destination in TBB, the
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// 'false' destination in FBB, and a list of operands that evaluate the
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// condition. These operands can be passed to other TargetInstrInfo
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// methods to create new branches.
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//
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// Note that removeBranch and insertBranch must be implemented to support
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// cases where this method returns success.
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//
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// If AllowModify is true, then this routine is allowed to modify the basic
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// block (e.g. delete instructions after the unconditional branch).
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//
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// The CFG information in MBB.Predecessors and MBB.Successors must be valid
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// before calling this function.
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bool SPIRVInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const {
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// We do not allow to restructure blocks by results of analyzeBranch(),
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// because it may potentially break structured control flow and anyway
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// doubtedly may be useful in SPIRV, including such reasons as, e.g.:
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// 1) there is no way to encode `if (Cond) then Stmt` logic, only full
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// if-then-else is supported by OpBranchConditional, so if we supported
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// splitting of blocks ending with OpBranchConditional MachineBasicBlock.cpp
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// would expect successfull implementation of calls to insertBranch() setting
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// FBB to null that is not feasible; 2) it's not possible to delete
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// instructions after the unconditional branch, because this instruction must
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// be the last instruction in a block.
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return true;
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}
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// Remove the branching code at the end of the specific MBB.
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// This is only invoked in cases where analyzeBranch returns success. It
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// returns the number of instructions that were removed.
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// If \p BytesRemoved is non-null, report the change in code size from the
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// removed instructions.
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unsigned SPIRVInstrInfo::removeBranch(MachineBasicBlock &MBB,
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int * /*BytesRemoved*/) const {
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MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
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if (I == MBB.end())
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return 0;
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if (I->getOpcode() == SPIRV::OpBranch) {
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I->eraseFromParent();
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return 1;
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}
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return 0;
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}
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// Insert branch code into the end of the specified MachineBasicBlock. The
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// operands to this method are the same as those returned by analyzeBranch.
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// This is only invoked in cases where analyzeBranch returns success. It
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// returns the number of instructions inserted. If \p BytesAdded is non-null,
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// report the change in code size from the added instructions.
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//
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// It is also invoked by tail merging to add unconditional branches in
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// cases where analyzeBranch doesn't apply because there was no original
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// branch to analyze. At least this much must be implemented, else tail
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// merging needs to be disabled.
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//
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// The CFG information in MBB.Predecessors and MBB.Successors must be valid
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// before calling this function.
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unsigned SPIRVInstrInfo::insertBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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ArrayRef<MachineOperand> Cond,
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const DebugLoc &DL,
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int * /*BytesAdded*/) const {
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if (!TBB)
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return 0;
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BuildMI(&MBB, DL, get(SPIRV::OpBranch)).addMBB(TBB);
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return 1;
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}
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void SPIRVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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const DebugLoc &DL, Register DestReg,
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Register SrcReg, bool KillSrc,
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bool RenamableDest, bool RenamableSrc) const {
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// Actually we don't need this COPY instruction. However if we do nothing with
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// it, post RA pseudo instrs expansion just removes it and we get the code
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// with undef registers. Therefore, we need to replace all uses of dst with
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// the src register. COPY instr itself will be safely removed later.
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assert(I->isCopy() && "Copy instruction is expected");
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auto DstOp = I->getOperand(0);
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auto SrcOp = I->getOperand(1);
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assert(DstOp.isReg() && SrcOp.isReg() &&
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"Register operands are expected in COPY");
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auto &MRI = I->getMF()->getRegInfo();
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MRI.replaceRegWith(DstOp.getReg(), SrcOp.getReg());
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}
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